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4.2 Kirchhoff's Voltage Law (KVL)

4.2 Kirchhoff's Voltage Law (KVL)

Written by the Fiveable Content Team • Last updated August 2025
Written by the Fiveable Content Team • Last updated August 2025
🔌Intro to Electrical Engineering
Unit & Topic Study Guides

Kirchhoff's Voltage Law Basics

Kirchhoff's Voltage Law (KVL) states that the sum of all voltages around any closed loop in a circuit equals zero. This is one of the most fundamental tools in circuit analysis because it lets you write equations to find unknown voltages and currents in any circuit, no matter how complex.

Fundamental Concepts of KVL

The core idea behind KVL comes from conservation of energy. As charge moves around a complete loop in a circuit, it gains energy from sources (like batteries) and loses energy in components (like resistors). By the time it returns to where it started, the total energy gained must equal the total energy lost. In voltage terms:

V=0\sum V = 0

This means the algebraic sum of all voltage rises and drops around any closed loop is zero.

A few key definitions:

  • A closed loop is any complete path in a circuit where the starting and ending points are the same.
  • A voltage drop occurs across a passive component (resistor, inductor, capacitor, diode) as it consumes energy from the circuit.
  • A voltage rise occurs across an active component (battery, voltage source) as it supplies energy to the circuit.

Algebraic Sum in KVL

"Algebraic sum" means you account for both the magnitude and the sign (polarity) of each voltage as you go around the loop. Here's how to apply it:

  1. Pick a loop in the circuit.

  2. Choose a reference direction to traverse the loop (clockwise or counterclockwise). Either choice works as long as you stay consistent for that loop.

  3. Walk around the loop, and at each component, note the voltage:

    • If you cross from + to (in your direction of travel), that voltage is a drop, so assign it a positive value.
    • If you cross from to +, that voltage is a rise, so assign it a negative value (or vice versa, depending on your convention; just be consistent).
  4. Sum all the voltages you recorded. The total must equal zero.

For example, consider a simple loop with a 12 V battery and two resistors. If the voltage drops across the resistors are V1V_1 and V2V_2, KVL gives you:

12V+V1+V2=0-12\,\text{V} + V_1 + V_2 = 0

This tells you that V1+V2=12VV_1 + V_2 = 12\,\text{V}. The drops across the resistors must add up to the source voltage.

Fundamental Concepts of KVL, Kirchhoff’s Rules | Boundless Physics

KVL Applications

Sign Convention in KVL

A consistent sign convention keeps your equations correct. The most common approach in introductory circuits is the passive sign convention:

  • For a passive component (resistor, capacitor, inductor): the current enters the positive terminal. The voltage drop across it is positive when your reference direction matches the current flow.
  • For an active component (battery, voltage source): the current exits the positive terminal. The voltage rise is positive when your reference direction goes from − to +.

As long as you stick with one convention throughout a problem, your signs will work out. If you accidentally flip a sign, you'll get a negative answer for that variable, which just means the actual polarity is opposite to what you assumed. That's not an error; it's the math correcting your assumption.

Fundamental Concepts of KVL, 21.3 Kirchhoff’s Rules – College Physics

Potential Difference and KVL

KVL is rooted in the concept of potential difference (voltage between two points). A key property of voltage in circuits: the potential difference between two points is the same regardless of which path you take between them.

KVL is a direct consequence of this. In a closed loop, the start and end points are the same, so the potential difference between them is zero. That's why all the voltage gains and losses around the loop must cancel out.

This also means that if two different paths connect the same two nodes, the total voltage along each path must be equal. You can use this fact to write KVL equations even in circuits with multiple branches.

Mesh Analysis Using KVL

Mesh analysis is a systematic technique that applies KVL to solve for currents in planar circuits (circuits that can be drawn flat without any wires crossing).

Here's the process:

  1. Identify the meshes. A mesh is the smallest loop in the circuit that doesn't contain any other loop inside it.
  2. Assign a mesh current to each mesh. By convention, these are usually drawn clockwise, but the direction is arbitrary.
  3. Apply KVL to each mesh. Write a voltage equation around each mesh using the mesh currents. When two meshes share a component, the voltage across that component depends on the difference of the two mesh currents.
  4. Solve the system of equations. You'll get one equation per mesh. Solve them simultaneously (substitution, elimination, or matrices) to find each mesh current.

For example, in a circuit with two meshes sharing a resistor R2R_2, the KVL equation for mesh 1 might look like:

Vs+I1R1+(I1I2)R2=0-V_s + I_1 R_1 + (I_1 - I_2) R_2 = 0

Mesh analysis is especially useful because it often requires fewer equations than other methods like node-voltage analysis, particularly in circuits with many loops and fewer nodes.