12.2 DC analysis and biasing of FETs

FET Operating Regions

FETs control current flow using an electric field at the gate, and they behave very differently depending on the voltages applied to their terminals. The three operating regions describe these different behaviors. Getting comfortable with these regions is essential because DC biasing is all about placing the FET in the right one.

Saturation Region and Drain Current Equation

A FET operates in the saturation region when the channel is pinched off near the drain. The condition for this is:

$V_{DS} \geq V_{GS} - V_T$

Once in saturation, the drain current $I_D$ becomes largely independent of $V_{DS}$ and is controlled almost entirely by $V_{GS}$. That's what makes this region useful for amplification: small changes in gate voltage produce proportional changes in drain current.

The saturation drain current equation is:

$I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2$

where:

• $\mu_n$ = electron mobility (how easily carriers move through the channel)
• $C_{ox}$ = oxide capacitance per unit area (depends on the gate insulator thickness)
• $W$ = channel width, $L$ = channel length
• $V_T$ = threshold voltage (the minimum $V_{GS}$ needed to form a conducting channel)

The ratio $\frac{W}{L}$ is a design parameter. A wider or shorter channel means more current for the same gate voltage. You'll sometimes see $k_n = \mu_n C_{ox} \frac{W}{L}$ grouped together as the transconductance parameter, which simplifies the equation to $I_D = \frac{1}{2} k_n (V_{GS} - V_T)^2$.

Notice the squared term: drain current has a nonlinear (quadratic) relationship with gate voltage in saturation. This matters for amplifier design and distortion analysis.

Linear Region and Cutoff Region

Linear (Triode) Region: When $V_{DS} < V_{GS} - V_T$, the channel isn't pinched off, and the FET behaves somewhat like a voltage-controlled resistor. Drain current depends on both $V_{GS}$ and $V_{DS}$:

$I_D = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_T)V_{DS} - \frac{1}{2}V_{DS}^2\right]$

For very small $V_{DS}$, the $\frac{1}{2}V_{DS}^2$ term becomes negligible, and the FET acts nearly like a linear resistor. This is why the region is called "linear" (or sometimes "ohmic"). It's the region used when a MOSFET operates as an analog switch or a pass transistor.

Cutoff Region: When $V_{GS} < V_T$, no conducting channel forms. The drain current is essentially zero, and the FET acts as an open switch. This is the "off" state used in digital logic gates and switching applications.

DC Biasing Techniques

The goal of DC biasing is to set a stable operating point (Q-point) so the FET sits in the correct region under no-signal conditions. A well-chosen Q-point keeps the transistor in saturation for amplifiers or ensures reliable switching between cutoff and linear for digital circuits.

Load Line Analysis and Q-Point

Load line analysis is a graphical method for finding the Q-point. Here's how it works:

1. Write the KVL equation around the drain-source loop. For a basic common-source circuit with a drain resistor $R_D$ and supply $V_{DD}$, this gives: $V_{DS} = V_{DD} - I_D R_D$

2. Plot this equation on the FET's $I_D$ vs. $V_{DS}$ output characteristic curves. It's a straight line (the "load line") with:

   • $V_{DS}$-intercept at $V_{DD}$ (when $I_D = 0$)
   • $I_D$-intercept at $\frac{V_{DD}}{R_D}$ (when $V_{DS} = 0$)

3. Find the intersection of the load line with the output curve corresponding to your gate bias voltage. That intersection is the Q-point, giving you the DC values of $I_D$ and $V_{DS}$.

The Q-point should sit in the middle of the saturation region for a Class A amplifier, giving maximum symmetric signal swing before clipping. For switching applications, you'd bias the FET to toggle between cutoff and the linear region.

Self-Bias and Voltage-Divider Bias

Self-Bias is the simplest biasing approach. A resistor $R_S$ is placed between the source terminal and ground, with the gate connected to ground through a large resistor $R_G$ (which draws negligible current).

• As $I_D$ flows through $R_S$, it creates a voltage $V_S = I_D R_S$ at the source.
• Since the gate is at 0 V (through $R_G$), the gate-to-source voltage becomes $V_{GS} = -I_D R_S$.
• This negative feedback is self-correcting: if $I_D$ tries to increase, $V_{GS}$ becomes more negative, which reduces $I_D$ back toward the design value.

Self-bias works well for JFETs and depletion-mode MOSFETs (which conduct at $V_{GS} = 0$). It won't work for enhancement-mode MOSFETs, which need a positive $V_{GS}$ to turn on.

Voltage-Divider Bias uses two resistors ($R_1$ and $R_2$) to set a specific DC voltage at the gate:

$V_G = V_{DD} \frac{R_2}{R_1 + R_2}$

Combined with a source resistor $R_S$, the gate-to-source voltage is:

$V_{GS} = V_G - I_D R_S$

This configuration works for enhancement-mode MOSFETs because you can set $V_G$ above the threshold voltage. It also provides better Q-point stability than self-bias because the gate voltage is fixed by the resistor ratio and is relatively independent of FET parameter variations (like shifts in $V_T$ due to temperature or manufacturing tolerances).

Constant-Current Bias

Constant-current bias replaces the source or drain resistor with an active current source, which forces $I_D$ to a fixed value regardless of FET parameter variations.

• The current source can be built from a BJT current mirror or another FET configured as a current source.
• Because $I_D$ is held constant, the Q-point is extremely stable. Variations in $V_T$ or $k_n$ simply shift $V_{GS}$ slightly rather than changing the operating current.
• This technique is common in high-performance and integrated circuit designs (such as RF amplifiers and op-amp input stages) where Q-point drift would degrade performance.

The tradeoff is added complexity: you need extra transistors and possibly a reference voltage to build the current source. For many discrete-component circuits, voltage-divider bias is "good enough," but constant-current bias is the go-to choice when stability and linearity really matter.