11.2 DC biasing and load line analysis

Biasing Circuits

DC biasing sets the transistor's steady-state conditions so it operates in the active region, where it can actually amplify signals. Without proper biasing, a BJT can sit in cutoff (off) or saturation (fully on), neither of which is useful for amplification. The biasing circuit determines the base current, which in turn controls the collector current and the voltage across the transistor.

Fixed Bias Configuration

This is the simplest way to bias a BJT. A single base resistor $R_B$ connects the base terminal to a DC supply voltage $V_{CC}$. The base current is:

$I_B = \frac{V_{CC} - V_{BE}}{R_B}$

where $V_{BE}$ is the base-emitter voltage (roughly 0.7 V for silicon BJTs). The collector current follows from the transistor's current gain:

$I_C = \beta I_B$

A collector resistor $R_C$ then limits the collector current and sets the collector-emitter voltage $V_{CE}$.

The big drawback of fixed bias is that $\beta$ varies significantly between individual transistors and with temperature. Since $I_C$ depends directly on $\beta$, the Q-point shifts whenever $\beta$ changes. This makes fixed bias unstable for practical designs.

Voltage Divider Bias Configuration

This is the most commonly used biasing configuration because it largely eliminates the dependence on $\beta$. Two resistors, $R_1$ and $R_2$, form a voltage divider from $V_{CC}$ to ground, setting the base voltage to approximately:

$V_B \approx V_{CC} \cdot \frac{R_2}{R_1 + R_2}$

An emitter resistor $R_E$ is included, and the emitter voltage follows the base voltage:

$V_E = V_B - V_{BE}$

The emitter current (and therefore the collector current, since $I_C \approx I_E$) is then:

$I_C \approx \frac{V_E}{R_E} = \frac{V_B - V_{BE}}{R_E}$

Notice that $\beta$ doesn't appear in this expression. As long as the divider current is much larger than the base current (the "stiff divider" condition), the Q-point stays nearly constant regardless of $\beta$ variations or temperature changes. The emitter resistor $R_E$ provides negative feedback: if $I_C$ tries to increase, $V_E$ rises, which reduces $V_{BE}$ and pulls $I_C$ back down.

Emitter Bias Configuration

Sometimes called emitter-stabilized bias, this configuration adds an emitter resistor $R_E$ to the fixed bias circuit. The resistor introduces the same negative feedback described above, improving stability over plain fixed bias.

• The voltage drop across $R_E$ reduces the effective $V_{BE}$, providing self-correction against current changes.
• A bypass capacitor $C_E$ is often placed in parallel with $R_E$. For DC, the capacitor is an open circuit, so the stabilizing effect of $R_E$ remains. For AC signals, the capacitor shorts out $R_E$, preventing it from reducing the amplifier's voltage gain.

Collector Feedback Bias Configuration

Here, a feedback resistor $R_F$ connects the collector directly back to the base. This creates a self-correcting loop:

1. If $I_C$ increases, the voltage drop across $R_C$ increases.
2. That causes $V_C$ to decrease.
3. Since $R_F$ connects to the collector, the base voltage also decreases.
4. Lower base voltage means less $I_B$, which pulls $I_C$ back down.

This negative feedback stabilizes the Q-point without needing a voltage divider network. It's a good middle ground between the simplicity of fixed bias and the stability of voltage divider bias.

Operating Point Analysis

Q-Point and Load Line

The Q-point (quiescent point) is the DC operating point of the transistor when no AC signal is applied. It's defined by two values: $V_{CE}$ and $I_C$. Choosing the right Q-point matters because it determines how much signal swing the amplifier can handle before clipping.

The load line is a straight line drawn on the transistor's output characteristic curves (the $I_C$ vs. $V_{CE}$ graph). It represents every possible combination of $V_{CE}$ and $I_C$ that the external circuit allows. The Q-point sits where the load line intersects the curve for the actual base current $I_B$.

How to Draw the DC Load Line

Start with KVL around the collector-emitter loop:

$V_{CC} = I_C R_C + V_{CE}$

(If there's an emitter resistor, replace $R_C$ with $R_C + R_E$.) This is a linear equation in $I_C$ and $V_{CE}$, so it plots as a straight line. You only need two points:

1. $V_{CE}$-axis intercept: Set $I_C = 0$. Then $V_{CE} = V_{CC}$. This is the cutoff point.
2. $I_C$-axis intercept: Set $V_{CE} = 0$. Then $I_C = V_{CC} / R_C$. This is the saturation point.

Connect these two points with a straight line. The slope is $-1/R_C$.

AC Load Line

When an AC signal is present, coupling capacitors and external load resistors change the effective resistance the transistor sees. The AC load line has a steeper slope of:

$-\frac{1}{R_C \| R_L}$

where $R_C \| R_L$ is the parallel combination of the collector resistor and the external load. The AC load line passes through the Q-point but has a different slope than the DC load line. It shows the range of $V_{CE}$ and $I_C$ swing during signal amplification.

Bias Stability

Stability Factor

The stability factor $S$ measures how sensitive the collector current is to changes in transistor parameters. It's commonly defined with respect to $\beta$ as:

$S = \frac{\Delta I_C}{\Delta \beta}$

A smaller $S$ means the Q-point barely moves when $\beta$ changes, which is what you want. Another common definition relates $S$ to changes in the leakage current $I_{CO}$:

$S = \frac{\Delta I_C}{\Delta I_{CO}}$

For an ideal, perfectly stable circuit, $S = 1$. For fixed bias, $S$ can approach $\beta + 1$, which is very poor.

Here's how the configurations compare in terms of stability:

The voltage divider configuration with a properly chosen $R_E$ gives the best stability for most practical amplifier designs. That's why it's the default choice in many circuits you'll encounter.