16.1 Flip-flops and latches

Flip-flops and latches are the building blocks of sequential logic circuits. These devices store one bit of digital information, allowing circuits to "remember" previous states and make decisions based on past inputs.

Understanding flip-flops and latches is crucial for designing memory elements and synchronous systems. This section covers the main types of latches and flip-flops, how they're triggered, and the timing constraints you need to respect for reliable circuit operation.

Latches and Flip-flops

Before diving into specific types, here's the key distinction: latches are level-triggered (they respond whenever an enable signal is active), while flip-flops are edge-triggered (they only respond at the instant a clock signal transitions). This difference matters a lot for how you use them in circuit design.

SR Latch

The SR latch is the simplest memory element. It's built from two cross-coupled NOR gates (or NAND gates, with inverted logic). It has two inputs: Set (S) and Reset (R).

• S=1, R=0: The latch is set, so $Q=1$
• S=0, R=1: The latch is reset, so $Q=0$
• S=0, R=0: The latch holds its previous state
• S=1, R=1: This is the invalid (forbidden) state. Both outputs try to go to the same value, and when you release both inputs simultaneously, the result is unpredictable. Always avoid this combination in your designs.

The SR latch is useful when you need an output to stay latched even after the input that caused it is removed, like a simple alarm circuit that stays on after being triggered.

D Latch

The D latch solves the SR latch's invalid-state problem by using a single data input (D) and an enable input (E).

• When E=1, the output $Q$ follows $D$ directly. This is called being transparent.
• When E=0, the latch holds whatever value $Q$ had when $E$ went low, regardless of what $D$ does afterward.

Think of it like a gate: while the gate is open (E=1), data passes through freely. Once the gate closes (E=0), the last value is locked in.

D Flip-flop

The D flip-flop is the edge-triggered version of the D latch, and it's the most commonly used flip-flop in synchronous digital design.

• It captures the value of $D$ only at the active clock edge (rising or falling, depending on the design).
• Between clock edges, the output $Q$ stays stable no matter what $D$ does.

This is a big advantage over the D latch: because the output only updates at one precise moment per clock cycle, you avoid the transparency problem where input glitches can pass through to the output.

JK Flip-flop

The JK flip-flop has two inputs, J (set) and K (reset), and it improves on the SR flip-flop by defining behavior for all input combinations:

• J=1, K=0: Flip-flop is set ($Q=1$) on the active clock edge
• J=0, K=1: Flip-flop is reset ($Q=0$) on the active clock edge
• J=0, K=0: Flip-flop holds its previous state
• J=1, K=1: Flip-flop toggles ($Q$ flips to its complement) on each active clock edge

That toggle behavior is what makes the JK flip-flop so useful in counters and state machines. There's no invalid state.

T Flip-flop

The T (toggle) flip-flop is the simplest flip-flop for counting applications. It has a single input, T:

• When T=1, the output toggles on each active clock edge.
• When T=0, the output holds its previous state.

You can build a T flip-flop from a JK flip-flop by tying $J$ and $K$ together. T flip-flops are the core component in frequency dividers (each stage divides the clock frequency by 2) and binary counters.

Triggering Methods

Edge-Triggered

Flip-flops use edge triggering, meaning they respond only at the instant the clock signal transitions:

• Rising edge-triggered: Output updates only on the low-to-high (0→1) transition of the clock.
• Falling edge-triggered: Output updates only on the high-to-low (1→0) transition of the clock.

Because the output changes at only one specific moment per cycle, edge triggering provides tight synchronization across all flip-flops in a circuit. This is why edge-triggered flip-flops dominate synchronous sequential design.

Level-Triggered

Latches use level triggering, meaning they respond throughout the entire time the enable/clock signal is active:

• When the enable is high, the latch is transparent and the output tracks the input.
• When the enable is low, the latch holds its state.

The risk here is that any noise or glitch on the input while the latch is transparent will pass straight through to the output. This is why latches are less common in synchronous designs, though they're still used for temporary data storage and in some asynchronous circuits.

Clock Signal

The clock signal is a periodic waveform that coordinates when all the flip-flops in a circuit update. A few key terms:

• Rising edge: The 0→1 transition
• Falling edge: The 1→0 transition
• Clock period ($T$): The time between two consecutive rising edges (or two consecutive falling edges)
• Clock frequency ($f$): The number of cycles per second, measured in Hz. Related to period by $f = \frac{1}{T}$

For example, a clock with a period of 10 ns has a frequency of $\frac{1}{10 \times 10^{-9}} = 100 \text{ MHz}$.

Timing Constraints

Timing constraints define the windows during which input data must be stable relative to the clock edge. Violating them can cause metastability, where the flip-flop's output gets stuck in an undefined state between 0 and 1.

Setup Time

Setup time ($t_{setup}$) is the minimum time the input data must be stable before the active clock edge arrives.

If you change the input too close to the clock edge, the flip-flop may not capture the correct value. In modern digital circuits, $t_{setup}$ is typically a few nanoseconds.

Hold Time

Hold time ($t_{hold}$) is the minimum time the input data must remain stable after the active clock edge.

Even though the clock edge has already passed, the flip-flop's internal circuitry still needs a brief moment to finish latching the data. $t_{hold}$ is usually shorter than $t_{setup}$, often in the range of picoseconds to low nanoseconds.