13.3 Digital logic levels and noise margins

Logic Levels and States

Digital logic levels define the voltage ranges that represent binary 1 and 0 in a circuit. Every digital system needs clear rules about what counts as "high" and what counts as "low," because real voltages aren't perfectly clean. Without these defined ranges, circuits couldn't reliably tell the difference between a 1 and a 0.

Logic Levels and Voltage Thresholds

A logic high (1) is any voltage above a specified threshold, representing "true" or "on." A logic low (0) is any voltage below a different threshold, representing "false" or "off." The gap between these two thresholds is a forbidden zone where the signal is ambiguous and shouldn't linger.

Four key voltage parameters define these thresholds:

• $V_{IH}$ (Input High): the minimum input voltage that the receiving gate will reliably interpret as a logic 1
• $V_{IL}$ (Input Low): the maximum input voltage that the receiving gate will reliably interpret as a logic 0
• $V_{OH}$ (Output High): the minimum output voltage a gate guarantees when driving a logic 1
• $V_{OL}$ (Output Low): the maximum output voltage a gate guarantees when driving a logic 0

Notice the pattern: the output specs ($V_{OH}$, $V_{OL}$) are always "better" than the input specs ($V_{IH}$, $V_{IL}$). That built-in gap is what gives the system room to handle noise.

Why Defined Logic Levels Matter

Standardized voltage thresholds let chips from different manufacturers work together. If every company picked its own voltage ranges, you couldn't mix and match components on a circuit board. Defined logic levels also prevent problems like crosstalk (signals interfering with neighboring traces) and unwanted transitions between states, because there's a clear buffer zone between what counts as high and what counts as low.

Noise Margins and Fan-out

Noise Margins

Noise margins tell you how much unwanted voltage fluctuation a signal can pick up and still be read correctly. They're the safety cushion between what a gate outputs and what the next gate needs to see.

There are two noise margins to know:

Noise Margin High (NMH):

$NMH = V_{OH} - V_{IH}$

This is the difference between the weakest logic-high output and the minimum voltage the input needs to recognize a 1. A larger $NMH$ means the signal can tolerate more positive noise before being misread.

Noise Margin Low (NML):

$NML = V_{IL} - V_{OL}$

This is the difference between the highest voltage the input still reads as a 0 and the worst-case logic-low output. A larger $NML$ means the signal can tolerate more noise pulling a low signal upward.

For example, in standard TTL: $V_{OH} = 2.4\text{V}$, $V_{IH} = 2.0\text{V}$, $V_{IL} = 0.8\text{V}$, $V_{OL} = 0.4\text{V}$. That gives you $NMH = 0.4\text{V}$ and $NML = 0.4\text{V}$. Any noise spike smaller than 0.4V won't cause a misread.

Adequate noise margins are especially important for long signal paths and noisy environments where voltage fluctuations are more likely.

Fan-out

Fan-out is the maximum number of input gates that a single output can drive while still maintaining valid logic levels. It's determined by how much current the output can source (for a high) or sink (for a low), compared to how much current each input draws.

• Higher fan-out means one output can connect to more inputs without needing extra buffers
• Exceeding the fan-out limit causes the output voltage to sag (for highs) or rise (for lows), potentially pushing it into the forbidden zone
• This leads to signal degradation, increased propagation delay, and possible logic errors

When designing systems with many interconnected gates, you need to check that no output is overloaded. If it is, add a buffer to restore the signal.

Logic Families and Performance

Logic Families Overview

A logic family is a group of ICs that share the same electrical characteristics, voltage levels, and fabrication technology. Different families make different tradeoffs between speed, power consumption, noise immunity, and cost. The two most important families for this course are TTL and CMOS.

Transistor-Transistor Logic (TTL)

TTL uses bipolar junction transistors (BJTs) to implement logic functions. It typically runs on a 5V supply with these standard levels:

• $V_{OH} \geq 2.4\text{V}$, $V_{OL} \leq 0.4\text{V}$
• $V_{IH} = 2.0\text{V}$, $V_{IL} = 0.8\text{V}$

TTL offers fast switching speeds and decent noise immunity, but draws moderate power even when idle (because BJTs conduct small currents in both states). Sub-families like 74LS (Low-power Schottky) and 74ALS (Advanced Low-power Schottky) improve the speed-to-power ratio while staying compatible with standard TTL voltage levels.

Complementary Metal-Oxide-Semiconductor (CMOS)

CMOS uses complementary pairs of p-channel and n-channel MOSFETs. Its biggest advantage is extremely low static power consumption, since in a steady state, one of the two transistors is always off, blocking current flow.

Key characteristics:

• Supply voltage can range from about 3V to 15V, making CMOS very flexible
• Logic levels are typically defined as roughly 70% of $V_{DD}$ for $V_{IH}$ and 30% of $V_{DD}$ for $V_{IL}$, which gives CMOS excellent noise margins
• Sub-families like 74HC (High-speed CMOS) and 74HCT (High-speed CMOS, TTL-compatible) offer faster switching while keeping power low

Because CMOS inputs are essentially insulated gates with very high impedance, CMOS fan-out is typically much higher than TTL.

Propagation Delay

Propagation delay ($t_{pd}$) is the time it takes for a change at a gate's input to appear at its output. It's measured from the 50% point of the input transition to the 50% point of the output transition.

This delay sets the upper limit on how fast a digital system can run. If your clock period is shorter than the total propagation delay through a chain of gates, the circuit won't work correctly.

Typical values vary by family. For instance, 74HC gates have propagation delays around 8–15 ns, while older 74LS gates are in the 9–20 ns range. Faster families are essential for high-frequency designs, but they often trade off higher power consumption for that speed.