23.3 Hardware description languages (VHDL/Verilog)

Hardware Description Languages

Overview of HDLs

Hardware description languages (HDLs) let you describe digital circuits in code rather than drawing schematics by hand. This makes it far easier to design, test, and revise complex digital systems before committing to physical hardware.

The two dominant HDLs are:

• VHDL (VHSIC Hardware Description Language) — Originally developed for the U.S. Department of Defense. It's strongly typed and verbose, which makes designs explicit but also more wordy to write.
• Verilog — Developed around the same time with syntax closer to C. It tends to be more concise than VHDL, which many designers find faster to work with for smaller projects.

Both languages let you specify the behavior and structure of digital systems at various levels of abstraction, from high-level functional descriptions down to individual gate connections. They also support simulation and synthesis, meaning you can test your design virtually and then convert it into actual hardware.

Key Features of VHDL and Verilog

• Modular design — Complex systems get divided into smaller, manageable modules. You can design a module once and reuse it throughout a project.
• Concurrent and sequential constructs — Digital hardware operates in parallel (many things happen at the same time), so HDLs provide ways to describe both concurrent behavior (signals updating simultaneously) and sequential behavior (step-by-step processes like state machines).
• Familiar programming constructs — Data types, operators, and control structures (if/else, case statements, loops) work similarly to software programming languages, which helps when describing digital logic.
• Hierarchical design — You can nest modules inside other modules, building up complexity layer by layer while keeping each piece understandable on its own.

Modeling and Verification

Behavioral and Structural Modeling

HDLs support two main approaches to describing a circuit, and understanding the difference matters:

Behavioral modeling describes what a system does without specifying how it's built. You write code that captures the desired functionality using high-level constructs like arithmetic operations and conditional statements. For example, you might write that an output equals the sum of two inputs, without worrying about which specific adder circuit implements that sum.

Structural modeling describes how a system is built by specifying its components and their interconnections. Think of it like a netlist: you instantiate individual gates or modules and wire them together explicitly. This gives you precise control over the architecture but requires more detail.

Most real designs use a mix of both. You might model a top-level controller behaviorally while describing the datapath structurally.

Testbenches and Simulation

A testbench is a separate HDL file that wraps around your design to verify it works correctly. The testbench itself doesn't get synthesized into hardware; it exists purely for testing.

A typical testbench workflow:

1. Instantiate the design under test (DUT) — Connect your module's inputs and outputs to signals the testbench controls.
2. Generate stimulus — Apply a sequence of input values to the DUT. This might include clock signals, reset pulses, and various data patterns.
3. Observe outputs — Monitor what the DUT produces in response to each input combination.
4. Check correctness — Compare the actual outputs against expected values, either manually by reading waveforms or automatically with assertion statements in the testbench code.
5. Report results — Flag any mismatches so you can trace and fix bugs.

Simulation lets you analyze your design's behavior under many different conditions before any hardware is involved. Catching a logic error in simulation costs minutes; catching it after fabrication costs weeks or more.

Digital Logic Components

Combinational Logic Elements

Combinational circuits produce outputs that depend only on the current inputs. There's no memory involved: change the inputs, and the outputs update accordingly (after a small propagation delay).

• Logic gates are the fundamental building blocks, performing basic Boolean operations: AND, OR, NOT, XOR, NAND, NOR.
• Multiplexers (MUX) select one of several input signals and route it to a single output, based on select lines. A 4-to-1 MUX, for instance, chooses one of four inputs using two select bits.
• Decoders convert a binary input code into one active output line. A 3-to-8 decoder activates one of eight output lines based on a 3-bit input.
• Arithmetic circuits like adders and subtractors perform math on binary numbers. A full adder, for example, adds two bits plus a carry-in and produces a sum bit and a carry-out.

Sequential Logic Elements

Sequential circuits have memory: their outputs depend on both the current inputs and the previous state. This is what allows digital systems to store data and step through processes over time.

The core building block is the flip-flop, a circuit element that stores one bit of state and updates on a clock edge:

• D flip-flop — Captures the value on its D input at each clock edge. This is the most commonly used type.
• JK flip-flop — Has two inputs (J and K) that control set, reset, and toggle behavior.
• T flip-flop — Toggles its output on each clock edge when its T input is high.

By combining flip-flops with combinational logic, you build larger sequential components:

• Registers — Groups of flip-flops that store multi-bit values (e.g., an 8-bit register holds one byte).
• Counters — Cycle through a sequence of binary values, useful for timing and control.
• Finite state machines (FSMs) — Step through defined states based on inputs and current state. FSMs are central to designing controllers and protocol handlers.

Implementation

Synthesis and FPGA Programming

Once your HDL design simulates correctly, the next step is turning it into real hardware. Here's how that process works:

1. Synthesis — A synthesis tool reads your HDL code and converts it into a gate-level netlist, a description of logic gates and their connections. During this step, the tool optimizes the design for speed, area, or power based on constraints you provide.
2. Technology mapping — The synthesized netlist gets mapped to the specific resources available on your target device (e.g., the lookup tables and flip-flops inside an FPGA).
3. Place and route — The tool decides where each logic element goes on the chip and how the wiring between them is laid out.
4. Bitstream generation — The final output is a configuration file (bitstream) that programs the device.
5. Programming the FPGA — The bitstream is loaded onto the FPGA, configuring its logic blocks, interconnects, and I/O pins to implement your design.

Field Programmable Gate Arrays (FPGAs) are reconfigurable chips that can be reprogrammed as many times as needed. Unlike custom ASICs (Application-Specific Integrated Circuits), which are permanently fabricated for one design, FPGAs let you modify and update your circuit just by loading a new bitstream. This makes them ideal for prototyping, low-volume production, and designs that may need future updates.