12.5 Metallization and interconnects

Metallization and interconnects create the electrical wiring that ties individual transistors, resistors, and capacitors together into a working integrated circuit. Without them, you'd have billions of isolated devices on a chip doing nothing useful. As devices shrink and circuits grow more complex, the design of these metal layers becomes one of the biggest bottlenecks for performance and reliability.

Metallization in semiconductor devices

Metallization is the process of depositing metal layers onto a semiconductor substrate to form the electrical connections a circuit needs. These metal layers serve three main purposes:

• Contacts connect the metal wiring down to the transistor terminals (source, drain, gate).
• Interconnects are the horizontal metal lines that route signals and power between components.
• Bonding pads are large metal areas at the chip's edge where external wires attach to connect the chip to its package.

Together, these elements turn a collection of individual devices into a functional integrated circuit.

Interconnects in integrated circuits

Role of interconnects

Interconnects are the conductive pathways that carry signals and power between transistors, resistors, capacitors, and every other element on a chip. They directly affect three critical aspects of IC performance:

• Speed: Long or resistive interconnects slow down signal propagation.
• Power consumption: Charging and discharging the capacitance of interconnect lines burns energy.
• Reliability: Interconnects must survive years of current flow without breaking down.

As transistor counts climb into the billions, routing all the necessary connections becomes a massive design challenge. The interconnect network on a modern chip can contain kilometers of total wire length.

Interconnect materials

Interconnects are made from metals because of their high electrical conductivity. The most common choices are:

• Aluminum (Al): The traditional interconnect metal, easy to deposit and pattern. Still used in some applications.
• Copper (Cu): The current standard for most advanced chips. Lower resistivity than Al, which means less resistance and faster signals.
• Tungsten (W): Primarily used for vertical connections (vias and contacts) rather than long horizontal runs, because it fills narrow holes well.

The shift from aluminum to copper, which began in the late 1990s, was driven by copper's roughly 40% lower resistivity. That difference becomes critical as wires shrink.

Metal-semiconductor junctions

Schottky barrier

When a metal is placed in direct contact with a semiconductor, a potential energy barrier called a Schottky barrier forms at the interface. This barrier arises because the metal and semiconductor have different work functions (the energy needed to pull an electron out of the material).

A Schottky barrier creates a rectifying contact, meaning current flows easily in one direction but is blocked in the other. The barrier height controls how much voltage you need to turn the junction "on." Schottky diodes exploit this behavior for fast-switching applications, since they don't store minority carriers the way p-n junctions do.

Ohmic contacts

An ohmic contact is the opposite goal: you want a metal-semiconductor junction with a linear current-voltage relationship (following Ohm's law) and very low resistance. Every transistor needs ohmic contacts at its terminals so current can flow in and out freely.

The trick to making an ohmic contact is to heavily dope the semiconductor right at the contact region. Heavy doping makes the depletion region so thin that carriers can tunnel straight through the Schottky barrier, effectively eliminating it. Without good ohmic contacts, a device wastes energy and generates excess heat at every terminal.

Metal deposition techniques

Physical vapor deposition (PVD)

PVD converts a solid source material into vapor, which then condenses as a thin film on the wafer. Two common PVD methods:

• Evaporation: The source material is heated (often by an electron beam) until it vaporizes. Atoms travel in a straight line and condense on the substrate. Simple but gives poor coverage over steps and trenches.
• Sputtering: Energetic ions (usually argon) bombard a target, knocking atoms loose. Those atoms deposit on the substrate. Sputtering gives better coverage than evaporation and works with a wider range of materials.

Chemical vapor deposition (CVD)

CVD deposits films through chemical reactions of gaseous precursors on a heated substrate surface. The process works in three basic steps:

1. Precursor gases flow into the reaction chamber.
2. The gases react and decompose on the hot substrate surface.
3. A solid film forms while gaseous byproducts are pumped away.

CVD's biggest advantage is conformal coverage: it coats sidewalls and bottom surfaces of trenches much more evenly than PVD. Variants include low-pressure CVD (LPCVD) for high-quality films and plasma-enhanced CVD (PECVD), which uses plasma energy to allow deposition at lower temperatures.

Electroplating

Electroplating is the primary method for depositing thick copper interconnect layers. Here's how it works:

1. A thin copper seed layer is first deposited by PVD or CVD.
2. The wafer (acting as the cathode) is immersed in an electrolyte solution containing copper ions.
3. An external current drives copper ions to reduce and deposit onto the seed layer.
4. The copper fills trenches and vias from the bottom up.

Electroplating is cost-effective for thick films but only works on conductive surfaces, which is why that seed layer is essential.

Comparison of deposition methods

Multilevel metallization

Need for multilevel metallization

A single metal layer can't route all the connections a modern IC needs. Think of it like a city: you can't connect every building with roads on one level without running out of space. Multilevel metallization stacks multiple metal layers separated by insulating layers, typically 10 or more layers on advanced chips.

Lower metal layers (closest to the transistors) are thin and tightly spaced for local connections. Upper metal layers are thicker and wider, carrying power and long-distance signals with lower resistance.

Interlayer dielectrics

Interlayer dielectrics (ILDs) are the insulating layers that separate adjacent metal levels. They serve two purposes: electrical isolation and minimizing parasitic capacitance between metal lines.

Common ILD materials include:

• Silicon dioxide ($SiO_2$): The traditional choice, with $k \approx 3.9$.
• Silicon nitride ($Si_3N_4$): Often used as an etch stop or barrier layer.
• Low-k dielectrics: Materials with $k < 3.9$, used to reduce capacitance in advanced nodes.

Lower dielectric constant means less capacitance between wires, which translates directly to faster signals and lower power consumption.

Planarization techniques

After depositing each metal or dielectric layer, the wafer surface becomes uneven. You need to flatten it before adding the next layer, or you'll get poor coverage, voids, and broken connections above.

Chemical-mechanical polishing (CMP) is the standard planarization method. It presses the wafer face-down against a rotating pad with a chemically reactive slurry. The combination of chemical etching and mechanical abrasion removes high spots and produces a flat surface. CMP is essential to the damascene process used for copper interconnects, where copper is deposited into pre-etched trenches and then polished back to leave metal only in the trenches.

Interconnect scaling challenges

Resistance vs. interconnect dimensions

As wires shrink at each new technology node, their cross-sectional area decreases and resistance goes up. The relationship is straightforward:

$R = \rho \frac{L}{A}$

where $\rho$ is the metal's resistivity, $L$ is the wire length, and $A$ is the cross-sectional area. Cut the width and height of a wire in half, and the area drops by 4×, quadrupling the resistance for the same length.

At very small dimensions (below ~30 nm width), resistivity itself increases because electrons scatter off the wire's surfaces and grain boundaries more frequently. This size effect makes the scaling problem even worse than the simple formula predicts.

Capacitance vs. interconnect spacing

As wires move closer together, the capacitance between them increases:

$C = \frac{\varepsilon_0 \varepsilon_r A}{d}$

Here $\varepsilon_0$ is the permittivity of free space, $\varepsilon_r$ is the relative permittivity of the dielectric between the wires, $A$ is the overlapping area, and $d$ is the spacing. Halving the spacing doubles the capacitance.

Higher capacitance means more energy is needed to switch signals and more crosstalk between neighboring lines. This is why low-k dielectrics are so important at advanced nodes.

Impact on signal delay

Signal delay through an interconnect is governed by the RC time constant:

$\tau = RC$

Since both $R$ and $C$ increase as dimensions shrink, the delay grows rapidly. At older technology nodes, transistor switching speed was the bottleneck. At modern nodes (below ~90 nm), interconnect delay dominates. This is why so much engineering effort goes into interconnect materials and geometry optimization.

Reliability issues in metallization

Electromigration

Electromigration occurs when high-density electron flow gradually pushes metal atoms along the wire. Over time, atoms pile up in some spots (forming hillocks) and leave gaps in others (forming voids). Voids can break a wire (open circuit), and hillocks can bridge to a neighboring wire (short circuit).

The mean time to failure from electromigration is described by Black's equation:

$MTTF = A \cdot J^{-n} \cdot \exp\left(\frac{E_a}{kT}\right)$

where $J$ is the current density, $E_a$ is the activation energy for atomic migration, $k$ is Boltzmann's constant, $T$ is temperature, and $A$ and $n$ are empirically determined constants. The key takeaway: higher current density and higher temperature both dramatically shorten interconnect lifetime.

Stress migration

Stress migration is driven by mechanical stress rather than electron flow. Thermal expansion mismatch between the metal, the dielectric, and the silicon substrate creates stress during temperature cycling. Under sustained stress, metal atoms migrate along grain boundaries, forming voids that can eventually break the interconnect.

Stress migration is particularly problematic for wide copper lines and at via connections, and it worsens at elevated temperatures even without current flowing.

Strategies for improving reliability

• Use copper instead of aluminum (copper has better electromigration resistance).
• Add barrier and capping layers (e.g., tantalum/tantalum nitride, cobalt) to confine copper and block atomic migration paths.
• Design interconnects with lower current density by widening critical lines.
• Include redundant vias so that if one via fails, the connection still works.
• Apply design rules that limit maximum current density per wire.
• Perform accelerated reliability testing (high temperature, high current) to validate designs before production.

Advanced interconnect materials

Copper vs. aluminum

Copper replaced aluminum as the standard interconnect metal because of its significantly lower resistivity:

• Copper: $\rho_{Cu} = 1.68 \times 10^{-8} \; \Omega \cdot m$
• Aluminum: $\rho_{Al} = 2.82 \times 10^{-8} \; \Omega \cdot m$

That ~40% resistivity advantage allows narrower wires at the same resistance, or lower resistance at the same width. Copper also resists electromigration better than aluminum.

The tradeoff is that copper can't be patterned by traditional plasma etching the way aluminum can. Instead, copper interconnects use the damascene process: trenches are etched into the dielectric first, then copper is deposited to fill them, and CMP removes the excess. Copper also diffuses rapidly into silicon and $SiO_2$, poisoning transistors, so it must be fully enclosed in barrier layers (typically Ta/TaN).

Low-k dielectrics

Low-k dielectrics have a dielectric constant below that of $SiO_2$ ($k \approx 3.9$). Reducing $k$ directly reduces interconnect capacitance.

Examples include:

• Fluorinated silica glass (FSG): $k \approx 3.5$
• Organosilicate glass (OSG): $k \approx 2.7\text{–}3.0$
• Porous low-k materials: $k < 2.5$, achieved by introducing nanoscale pores

The challenge is that lower-k materials tend to be mechanically weaker and more sensitive to moisture and plasma damage. Integrating ultra-low-k dielectrics without cracking or delamination during CMP and packaging is one of the harder problems in back-end-of-line fabrication.

Carbon nanotubes and graphene

Carbon nanotubes (CNTs) and graphene are research-stage materials that could potentially supplement or replace copper in future interconnects.

• CNTs can carry enormous current densities (orders of magnitude higher than copper) without electromigration, and they have excellent thermal conductivity.
• Graphene offers extremely high electron mobility and thermal conductivity in a two-dimensional sheet.

Both materials face significant hurdles before they can be used in manufacturing: growing them precisely where needed, achieving low contact resistance to conventional metals, and scaling the process to full wafer production. They remain an active area of research rather than a near-term solution.

Characterization of interconnects

Resistance measurements

• Four-point probe: Measures sheet resistance ($R_s$) of a metal film by passing current through two outer probes and measuring voltage across two inner probes. This eliminates contact resistance from the measurement. Resistivity is then $\rho = R_s \times t$, where $t$ is the film thickness.
• Kelvin structures (e.g., cross-bridge resistors): Test structures built into the chip specifically to measure contact resistance between metal layers with high accuracy.
• Transmission line model (TLM): Uses a series of contacts with varying spacing to extract both sheet resistance and specific contact resistance from a single set of measurements.

Capacitance measurements

• Capacitance-voltage (C-V) measurements: A voltage sweep is applied across a metal-insulator-metal or metal-insulator-semiconductor structure, and the resulting capacitance is recorded. This reveals the dielectric constant and thickness of the insulating layer.
• Charge-based capacitance measurement (CBCM): Measures the charge needed to change the voltage across a test capacitor, enabling high-resolution extraction of parasitic capacitance between interconnect lines on actual chip structures.

Failure analysis techniques

When interconnects fail, engineers need to find out why. Common techniques include:

• Focused ion beam (FIB) milling: Cuts precise cross-sections through interconnect structures for inspection.
• Transmission electron microscopy (TEM): Provides atomic-resolution images of cross-sections to reveal voids, barrier integrity, and grain structure.
• Scanning electron microscopy (SEM): Images the surface to detect hillocks, voids, or cracking.
• Electrical tests: Current-voltage (I-V) measurements check for shorts and opens. Time-dependent dielectric breakdown (TDDB) tests apply sustained voltage stress to the dielectric to assess long-term reliability.

Results from failure analysis feed back into process optimization, helping engineers adjust deposition conditions, barrier layers, and design rules to prevent the same failures in production.