5.4 Capacitance-voltage characteristics

Capacitance-voltage (C-V) characteristics describe how the charge stored in a semiconductor junction changes with applied voltage. They're one of the most practical tools for probing what's happening inside a device: from doping profiles to oxide quality, C-V measurements give you quantitative access to parameters that are otherwise hidden.

This topic covers the two physical origins of junction capacitance (depletion and diffusion), how they combine, how measurement frequency matters, and how C-V data is used to extract real device parameters.

Capacitance in semiconductor devices

Capacitance in a semiconductor device isn't just a parasitic nuisance. It reflects real physics: charge is being stored and redistributed as you change the voltage. Two distinct mechanisms create this stored charge:

• Depletion capacitance comes from the fixed ionized dopant charges exposed as the depletion region widens or narrows.
• Diffusion capacitance comes from minority carriers injected into the quasi-neutral regions under forward bias.

Which mechanism dominates depends on the bias condition and the signal frequency, as you'll see below.

Depletion region capacitance

Depletion width vs applied voltage

The depletion region width responds directly to the applied voltage. Reverse bias pulls more carriers away from the junction, widening the depletion region. Forward bias pushes carriers toward the junction, narrowing it.

For a one-sided abrupt junction (where one side is much more heavily doped), the depletion width is:

$W_D = \sqrt{\frac{2\varepsilon_s(V_{bi} - V_A)}{qN}}$

where $\varepsilon_s$ is the semiconductor permittivity, $V_{bi}$ is the built-in potential, $V_A$ is the applied voltage (positive for forward bias, negative for reverse bias), $q$ is the elementary charge, and $N$ is the doping concentration on the lightly doped side.

Notice that $W_D$ grows as the square root of $(V_{bi} - V_A)$. So doubling the reverse bias doesn't double the depletion width.

Capacitance vs depletion width

The depletion region behaves like a parallel-plate capacitor: two conducting regions (the quasi-neutral p and n sides) separated by an insulating layer (the depleted region with no free carriers). The capacitance per unit area is:

$C_{dep} = \frac{\varepsilon_s}{W_D}$

Since $W_D$ appears in the denominator, a wider depletion region means less capacitance. This makes physical sense: the "plates" are farther apart, so less charge is stored per volt.

Capacitance-voltage relationship derivation

Substituting the expression for $W_D$ into the capacitance formula gives the C-V relationship directly:

$C_{dep} = \sqrt{\frac{q\varepsilon_s N}{2(V_{bi} - V_A)}}$

This tells you two things at a glance:

• Reverse bias ($V_A < 0$): the denominator grows, so capacitance drops.
• Forward bias ($V_A > 0$, but $V_A < V_{bi}$): the denominator shrinks, so capacitance rises.

The capacitance scales as $(V_{bi} - V_A)^{-1/2}$ for an abrupt junction. For a linearly graded junction, the exponent changes to $-1/3$. This distinction matters when you're extracting doping profiles from data.

Diffusion capacitance

Minority carrier distribution

Under forward bias, minority carriers are injected across the junction. On the n-side, you get excess holes; on the p-side, excess electrons. These injected carriers form a concentration profile that decays exponentially away from the junction edge.

The total injected minority carrier charge depends on the forward voltage. As you increase $V_A$, the injected charge increases exponentially (following the diode equation). Any change in voltage therefore causes a large change in stored charge, and that's capacitance.

Diffusion capacitance vs applied voltage

The diffusion capacitance is defined as the derivative of the stored minority carrier charge with respect to voltage:

$C_D = \frac{dQ}{dV} = \frac{I_0 \tau}{V_T} e^{V_A / V_T}$

where $I_0$ is the reverse saturation current, $\tau$ is the minority carrier lifetime, $V_T = kT/q$ is the thermal voltage (about 26 mV at room temperature), and $V_A$ is the applied forward voltage.

Because of the exponential dependence, $C_D$ is negligible under reverse bias but grows rapidly under forward bias. At moderate forward voltages, it easily exceeds the depletion capacitance by orders of magnitude.

Junction capacitance

Junction capacitance components

The total junction capacitance is the sum of both contributions:

$C_{total} = C_{dep} + C_D$

At any given bias point, one term usually dominates:

• Reverse bias and small forward bias: $C_{dep}$ dominates because $C_D$ is exponentially small.
• Moderate to large forward bias: $C_D$ dominates because it grows exponentially while $C_{dep}$ grows only as a power law.

Junction capacitance vs applied voltage

The overall C-V curve has a characteristic shape. Starting from large reverse bias and sweeping toward forward bias:

1. Capacitance is small and increases slowly (depletion capacitance regime, $C \propto (V_{bi} - V_A)^{-1/2}$).

2. Near $V_A = 0$, the curve steepens as the depletion region narrows.

3. Beyond a fraction of $V_{bi}$ in forward bias, diffusion capacitance takes over and the total capacitance rises exponentially.

The crossover between the two regimes depends on doping, carrier lifetime, and device geometry.

Measurement of C-V characteristics

Low and high frequency C-V

The measurement frequency determines which capacitance components you actually see:

• Low-frequency (quasi-static) C-V: The AC signal is slow enough that minority carriers can follow. Both depletion and diffusion capacitance are captured. Typical frequencies are below ~100 Hz for silicon.
• High-frequency C-V: The AC signal is too fast for minority carriers to respond. Only the depletion capacitance contributes. Typical measurement frequencies are 100 kHz to 1 MHz.

The transition frequency depends on the minority carrier lifetime $\tau$. Devices with longer lifetimes transition at lower frequencies.

Depletion and inversion regions in C-V

For MOS capacitors (not just p-n junctions), the C-V curve shows three distinct regions as gate voltage is swept:

• Accumulation: Majority carriers pile up at the surface. Capacitance equals the oxide capacitance $C_{ox}$ (maximum value).
• Depletion: Majority carriers are pushed away, forming a depletion region. Total capacitance is the series combination of $C_{ox}$ and $C_{dep}$, so it decreases.
• Inversion: Minority carriers form a layer at the surface. At low frequency, they can follow the signal and capacitance returns to $C_{ox}$. At high frequency, they can't follow, and capacitance stays at its minimum value.

The transition from depletion to inversion occurs when the surface potential $\phi_s$ equals twice the bulk Fermi potential $\phi_F$ (the strong inversion condition).

Applications of C-V characteristics

Determination of doping profile

The most common application of C-V data is extracting the doping profile. Rearranging the depletion capacitance formula gives:

$\frac{1}{C^2} = \frac{2(V_{bi} - V_A)}{q\varepsilon_s N}$

A plot of $1/C^2$ vs. $V_A$ yields a straight line for uniform doping. The slope gives you the doping concentration:

$N = \frac{-2}{q\varepsilon_s \cdot d(1/C^2)/dV}$

If the doping is non-uniform, the slope changes with voltage, and you can extract $N$ as a function of depth (since each voltage corresponds to a different depletion width).

Extraction of device parameters

Several device parameters come directly from C-V measurements:

• Built-in potential $V_{bi}$: the x-intercept of the $1/C^2$ vs. $V_A$ plot (extrapolated to $1/C^2 = 0$).
• Minority carrier lifetime $\tau$: extracted from the magnitude of diffusion capacitance under forward bias, using the $C_D$ expression.
• Oxide thickness (in MOS structures): calculated from the accumulation capacitance, since $C_{ox} = \varepsilon_{ox}/t_{ox}$.

C-V in MOS structures

C-V measurements are the standard characterization tool for MOS technology. From a single C-V sweep on a MOS capacitor, you can extract:

• Oxide thickness from $C_{ox}$ in accumulation
• Substrate doping from the slope in depletion
• Flatband voltage $V_{FB}$ from the transition point between accumulation and depletion
• Threshold voltage $V_T$ from the onset of inversion
• Oxide charge density from shifts in $V_{FB}$ relative to the ideal value
• Interface state density $D_{it}$ from the stretch-out of the C-V curve or from comparing low-frequency and high-frequency curves

Frequency effects on C-V characteristics

Low vs high frequency behavior

Frequency affects C-V curves because carrier generation and recombination take finite time. At low frequencies, minority carriers at the inversion layer can follow the AC signal, contributing to capacitance. At high frequencies, they can't.

The practical consequence: a high-frequency C-V curve shows capacitance dropping to a minimum in inversion and staying there, while a low-frequency curve shows capacitance rising back up to $C_{ox}$.

The crossover frequency scales roughly as $1/\tau$, where $\tau$ is the minority carrier generation lifetime. For high-quality silicon with long lifetimes, even 1 kHz can be "high frequency" in deep depletion.

Deep-level traps and interface states

Real devices have defects. Deep-level traps in the bulk and interface states at the semiconductor-oxide boundary can capture and emit carriers, adding extra capacitance contributions.

• Interface states cause the C-V curve to "stretch out" along the voltage axis. The curve looks like a smeared version of the ideal one.
• Deep-level traps respond at frequencies determined by their emission rates. At low frequencies they contribute to capacitance; at high frequencies they don't.
• Frequency dispersion (the C-V curve shifting with measurement frequency) is a signature of traps or interface states. Analyzing how the curve changes across a range of frequencies lets you map out trap density as a function of energy within the bandgap.

Small-signal capacitance models

Equivalent circuit representation

For circuit simulation, the junction is represented by a small-signal equivalent circuit. A typical model includes:

• Depletion capacitance $C_{dep}(V)$: a voltage-dependent capacitor
• Diffusion capacitance $C_D(V)$: also voltage-dependent, often modeled as a conductance $G_D$ in parallel with a capacitor
• Series resistance $R_s$: accounts for contact resistance and bulk semiconductor resistance

The series resistance matters at high frequencies because it creates an RC time constant that can distort the measured C-V curve. If $R_s$ is significant, you'll underestimate the true capacitance at high frequencies.

Capacitance in device modeling

Accurate capacitance modeling is essential for predicting switching speed, signal delay, and power dissipation in circuits. SPICE-level models (like BSIM for MOSFETs) include empirical capacitance-voltage relationships fitted to measured data.

These models capture the voltage dependence of both depletion and diffusion capacitance, along with parasitic capacitances (overlap capacitance, fringing capacitance). The physical basis is the same charge-storage physics covered above, but the expressions are often smoothed or parameterized to avoid numerical issues in simulation.