8.2 Threshold voltage and body effect

Threshold Voltage and Body Effect

Threshold voltage and body effect govern how MOSFETs turn on and how sensitive that turn-on behavior is to bias conditions. These two concepts are tightly linked: the body effect directly modifies the threshold voltage when a substrate bias is present. Getting a solid handle on both is essential for understanding MOSFET operation, circuit design trade-offs, and why real circuits don't always behave like the simplest textbook models suggest.

Threshold Voltage Fundamentals

The threshold voltage ($V_{th}$) is the minimum gate-to-source voltage needed to create a conducting inversion layer (channel) between the source and drain of a MOSFET. Below $V_{th}$, the transistor is nominally "off" (though subthreshold leakage still flows). Above it, the device turns on and conducts significant current.

$V_{th}$ directly controls several key device characteristics:

• On-off current ratio: A higher $V_{th}$ means less leakage in the off-state but also less drive current at a given gate overdrive.
• Subthreshold slope: How sharply the transistor transitions from off to on near threshold.
• Leakage current: Lower $V_{th}$ devices leak more current when they're supposed to be off.

Factors Affecting Threshold Voltage

Four main physical factors set the threshold voltage:

• Substrate doping concentration ($N_A$): Higher doping raises the Fermi potential and increases the charge in the depletion region, which pushes $V_{th}$ higher.
• Gate oxide thickness ($t_{ox}$): A thicker oxide reduces $C_{ox}$, meaning more gate voltage is needed to induce the same surface charge. This raises $V_{th}$.
• Gate-semiconductor work function difference ($\phi_{ms}$): Different gate materials (polysilicon, metals) create different built-in potentials relative to the substrate, shifting the flat-band voltage and therefore $V_{th}$.
• Temperature: As temperature increases, the Fermi level shifts and intrinsic carrier concentration rises. For most practical MOSFETs, $V_{th}$ decreases with increasing temperature (typically by about $-1$ to $-2 \text{ mV/°C}$).

Threshold Voltage Equation

For a long-channel MOSFET, the threshold voltage is:

$V_{th} = V_{FB} + 2\phi_F + \frac{\sqrt{2\varepsilon_s q N_A (2\phi_F)}}{C_{ox}}$

where:

• $V_{FB}$ = flat-band voltage (accounts for work function difference and oxide charges)
• $\phi_F$ = Fermi potential, $\phi_F = \frac{kT}{q}\ln\left(\frac{N_A}{n_i}\right)$
• $\varepsilon_s$ = permittivity of the semiconductor (for Si, $\approx 1.04 \times 10^{-12} \text{ F/cm}$)
• $q$ = electron charge ($1.6 \times 10^{-19} \text{ C}$)
• $N_A$ = acceptor doping concentration in the substrate
• $C_{ox}$ = gate oxide capacitance per unit area, $C_{ox} = \varepsilon_{ox}/t_{ox}$

The third term is the voltage needed to support the depletion charge at the onset of strong inversion ($2\phi_F$ of surface band bending). This is the term that the body effect will modify.

In short-channel devices, additional effects like drain-induced barrier lowering (DIBL) reduce the effective $V_{th}$ as drain voltage increases, and velocity saturation alters the current-voltage relationship. These require corrections to the long-channel equation.

Threshold Voltage Measurement Techniques

There are several standard ways to extract $V_{th}$ experimentally:

1. Linear extrapolation (I-V) method: Measure $I_D$ vs. $V_{GS}$ in the linear region at low $V_{DS}$. Plot $I_D$ vs. $V_{GS}$ and extrapolate the steepest linear portion to the $V_{GS}$ axis. The intercept gives $V_{th}$.
2. Constant current method: Define $V_{th}$ as the $V_{GS}$ at which $I_D$ reaches a specified reference current (e.g., $10 \text{ nA} \times W/L$). This is common in industry because it's simple and repeatable.
3. Transconductance ($g_m$) method: Plot the transconductance $g_m = \partial I_D / \partial V_{GS}$. The peak of $g_m$ in the linear region corresponds to the point of maximum mobility, and $V_{th}$ is extracted by extrapolating from that peak.
4. Subthreshold method: In the subthreshold regime, $\log(I_D)$ vs. $V_{GS}$ is approximately linear. Extrapolating this line can also yield a threshold estimate.

Each method gives slightly different values, so it's important to be consistent about which method you're using when comparing devices.

Body Effect Principles

The body effect (also called the substrate bias effect or back-gate effect) describes how applying a voltage between the source and the substrate (body) changes the threshold voltage. In many circuits, the source is not at the same potential as the body, so the body effect is something you'll encounter regularly.

Physically, the body effect arises because a source-to-body voltage $V_{SB}$ changes the amount of band bending needed to reach inversion, which changes the depletion charge under the gate.

Substrate Bias and Depletion Region

When you apply a reverse bias between the substrate and source ($V_{SB} > 0$ for an NMOS), you widen the depletion region beneath the channel. A wider depletion region means more exposed fixed charge (ionized acceptors in NMOS), which requires more gate voltage to compensate. The result: $V_{th}$ increases.

Conversely, a forward bias ($V_{SB} < 0$ for NMOS) narrows the depletion region and lowers $V_{th}$. However, forward biasing the body-source junction increases leakage and risks turning on the parasitic body-source diode, so this is used cautiously.

Body Effect on Threshold Voltage

The modified threshold voltage under a nonzero $V_{SB}$ is:

$V_{th}(V_{SB}) = V_{th0} + \gamma\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right)$

where:

• $V_{th0}$ = threshold voltage at $V_{SB} = 0$
• $\gamma$ = body effect coefficient
• $\phi_F$ = Fermi potential
• $V_{SB}$ = source-to-body voltage (positive for reverse bias in NMOS)

For example, if $V_{th0} = 0.5 \text{ V}$, $\gamma = 0.4 \text{ V}^{1/2}$, $\phi_F = 0.35 \text{ V}$, and $V_{SB} = 1 \text{ V}$:

$V_{th} = 0.5 + 0.4\left(\sqrt{0.7 + 1} - \sqrt{0.7}\right) = 0.5 + 0.4(1.304 - 0.837) = 0.5 + 0.187 = 0.687 \text{ V}$

That's a roughly 37% increase in threshold voltage from a 1 V body bias, which is significant.

Body Effect Coefficient

The body effect coefficient $\gamma$ quantifies how sensitive $V_{th}$ is to changes in $V_{SB}$:

$\gamma = \frac{\sqrt{2\varepsilon_s q N_A}}{C_{ox}}$

From this expression you can see two clear trends:

• Higher substrate doping ($N_A$) → larger $\gamma$ → stronger body effect. More dopant atoms mean more depletion charge to uncover per unit of band bending.
• Thinner gate oxide → larger $C_{ox}$ → smaller $\gamma$ → weaker body effect. A thinner oxide gives the gate better control, so the substrate bias has relatively less influence.

Typical values of $\gamma$ for bulk CMOS processes range from about $0.3$ to $0.8 \text{ V}^{1/2}$, depending on the technology node and doping.

Body Effect in Different Transistor Types

Not all transistor architectures experience the body effect equally:

• Bulk MOSFETs: Full body effect, since the thick substrate allows the depletion region to expand freely.
• Fully depleted SOI (FD-SOI): The thin silicon film is already fully depleted, so there's very little additional depletion charge to modulate. Body effect is greatly reduced. However, the back-gate bias through the buried oxide can still tune $V_{th}$.
• FinFETs and multi-gate devices: The gate wraps around the channel, providing strong electrostatic control. The body is narrow and largely controlled by the gate, so the substrate has minimal influence. Body effect is inherently small.
• Dynamic threshold MOSFETs (DTMOS): These intentionally tie the gate to the body so that $V_{th}$ drops as $V_{GS}$ increases. This exploits the body effect to get higher drive current at low supply voltages.

Threshold Voltage vs. Body Effect

Impact of Body Effect on Device Performance

The body effect has practical consequences across circuit types:

• Reduced drive current: Higher $V_{th}$ from body effect means less gate overdrive ($V_{GS} - V_{th}$) for the same $V_{GS}$, so the transistor conducts less current.
• Analog distortion: In a common-source amplifier, if the source voltage swings (as in a source follower), the body effect modulates $V_{th}$ during the signal swing. This introduces nonlinearity and reduces the voltage gain of source followers to below unity.
• Digital timing: In stacked transistor configurations (like a NAND gate), transistors farther from ground have nonzero $V_{SB}$. Their increased $V_{th}$ slows down the gate. A 4-input NAND is noticeably slower than a 4-input NOR in NMOS-heavy logic partly for this reason.
• Device mismatch: Variations in $\gamma$ across a chip translate into $V_{th}$ mismatch when $V_{SB} \neq 0$, degrading precision in matched-pair circuits.

Trade-offs in Threshold Voltage Design

Choosing $V_{th}$ involves a fundamental speed-vs-power trade-off:

• Lower $V_{th}$: More on-current, faster switching, but exponentially more subthreshold leakage. Leakage power can dominate in standby.
• Higher $V_{th}$: Less leakage, better noise margins, but slower switching and reduced current drive.

Modern processes offer multi-threshold voltage (multi-$V_t$) options. Critical-path transistors use low-$V_t$ for speed, while non-critical transistors use high-$V_t$ to save power. Adaptive body biasing takes this further by dynamically adjusting $V_{SB}$ to shift $V_{th}$ based on operating conditions (e.g., applying forward body bias during high-performance mode and reverse body bias during standby).

Techniques to Minimize Body Effect

• Lighter substrate doping or retrograde wells: Reduces $N_A$ near the surface, lowering $\gamma$.
• SOI or FinFET technology: Structurally eliminates or reduces the body effect, as discussed above.
• Forward body bias: Applying a small forward $V_{BS}$ can partially cancel the $V_{th}$ increase, but you must stay below the diode turn-on voltage (~0.3-0.4 V forward) to avoid excessive junction leakage.
• Circuit techniques: Triple-well processes allow independent body biasing of NMOS and PMOS. Source-body tied configurations (where possible) eliminate $V_{SB}$ entirely.

Applications of Threshold Voltage and Body Effect

Threshold Voltage in Analog Circuits

In analog design, $V_{th}$ sets the operating point. For a common-source amplifier, the input DC bias must exceed $V_{th}$ to keep the transistor in saturation. The body effect matters especially in:

• Source followers (common-drain): The output is at the source, so as the output swings, $V_{SB}$ changes and $V_{th}$ shifts. This reduces the voltage gain from the ideal value of 1 to roughly $\frac{g_m}{g_m + g_{mb}}$, where $g_{mb}$ is the body transconductance.
• Current mirrors: If source potentials differ between the reference and mirror transistors, body effect causes systematic current mismatch.
• Body-driven circuits: In ultra-low-voltage designs where $V_{DD}$ is near or below $V_{th}$, the body terminal can be used as the signal input instead of the gate, exploiting the body effect as the primary transconductance mechanism.

Body Effect in Digital Logic Design

In digital circuits, body effect shows up most clearly in stacked transistors. Consider a 4-input NMOS NAND gate: the transistor closest to ground has $V_{SB} = 0$, but each transistor above it has a progressively larger $V_{SB}$, raising its $V_{th}$. This means:

• Pull-down transitions are slower than in a single transistor.
• Transistors must be sized wider to compensate.
• Noise margins shift because the effective $V_{th}$ depends on the input pattern.

Body biasing in digital design is used to manage process corners and aging. Applying a slight forward body bias can recover speed in slow corners, while reverse body bias reduces leakage in fast corners or standby modes.

Threshold Voltage and Body Effect in Power Management

Power management heavily leverages $V_{th}$ and body effect:

• Dynamic voltage and frequency scaling (DVFS): Lowering $V_{DD}$ saves dynamic power ($\propto V_{DD}^2$), but $V_{th}$ must be low enough to maintain adequate drive current at the reduced supply.
• Power gating: Sleep transistors with high $V_{th}$ are used to cut off leakage paths to idle blocks. Their high $V_{th}$ ensures minimal leakage in the off-state.
• Adaptive body biasing (ABB): Sensors monitor process and temperature conditions, and a feedback loop adjusts $V_{SB}$ to keep $V_{th}$ at the optimal point. This compensates for manufacturing variation and temperature drift simultaneously.

Advanced Threshold Voltage Concepts

Threshold Voltage Variability and Matching

As transistors shrink, random dopant fluctuation (RDF) becomes a major source of $V_{th}$ variability. With only a few hundred dopant atoms in the channel of a modern device, statistical variation in their exact positions causes measurable $V_{th}$ differences between nominally identical transistors.

The standard deviation of $V_{th}$ mismatch between two adjacent devices scales as:

$\sigma(\Delta V_{th}) = \frac{A_{VT}}{\sqrt{WL}}$

where $A_{VT}$ is a technology-dependent constant (typically 1-5 mV·μm for modern processes) and $W$, $L$ are the transistor width and length. Larger transistors match better.

Layout techniques to improve matching include common-centroid placement, dummy devices at array edges, and consistent orientation of matched pairs relative to process gradients.

Threshold Voltage in High-Voltage Devices

High-voltage MOSFETs (LDMOSFETs, DeMOSFETs) face reliability challenges that affect $V_{th}$ over time:

• Hot carrier injection (HCI): High-energy carriers near the drain can become trapped in the gate oxide, causing $V_{th}$ to shift over the device lifetime.
• Bias temperature instability (BTI): Sustained gate bias at elevated temperature causes interface trap generation, gradually increasing $V_{th}$ (especially NBTI in PMOS).

These devices use optimized drift region doping, field plates, and thick gate oxides to manage electric fields and maintain $V_{th}$ stability.

Threshold Voltage in SOI and FinFET Technologies

• FD-SOI devices offer back-gate biasing through the buried oxide (BOX). Because the BOX is thicker than the front gate oxide, the back-gate has weaker control, but it provides a useful $V_{th}$ tuning knob (typically 80-100 mV/V of back-gate bias).
• FinFETs achieve $V_{th}$ targeting primarily through work function engineering of the metal gate rather than channel doping. This reduces RDF and improves variability. Multiple $V_t$ flavors are created by using different metal gate stacks or dipole layers at the gate oxide interface.

Threshold Voltage in Emerging Device Structures

Beyond conventional MOSFETs, threshold voltage engineering takes new forms:

• Tunnel FETs (TFETs): Turn-on is governed by band-to-band tunneling rather than thermionic emission. The "threshold" depends on band alignment at the source-channel junction, making it sensitive to material bandgap and heterojunction design.
• Negative capacitance FETs (NCFETs): A ferroelectric layer in the gate stack provides voltage amplification, enabling subthreshold swings below the 60 mV/decade room-temperature limit. This allows lower $V_{th}$ without the usual leakage penalty.
• 2D material FETs (e.g., $\text{MoS}_2$): $V_{th}$ can be tuned through electrostatic doping, choice of dielectric environment, and the number of atomic layers, offering flexibility not available in bulk silicon.

These emerging devices are still in the research stage, but they all require precise $V_{th}$ control to realize their potential advantages in low-power and high-performance applications.