Ion implantation introduces dopant ions into a semiconductor substrate by accelerating them as a beam and driving them into the material. This gives you far more control over where dopants end up and how many are placed compared to older doping methods like thermal diffusion from a gas source.

Advantages of ion implantation

Precise control over dopant concentration and depth distribution
Ability to introduce dopants below the substrate surface without affecting the top layer
Highly reproducible and uniform across the wafer
Compatible with planar processing and photolithography, so you can selectively dope through mask openings
Enables fabrication of advanced devices like MOSFETs and bipolar transistors with tightly controlled profiles

Limitations of ion implantation

Crystal damage from energetic ions displacing lattice atoms, requiring post-implantation annealing to repair
Depth of penetration is limited by ion energy; deep junctions may need very high-energy implants
Risk of contamination from the ion source or beam line components
High capital cost for implantation equipment

Ion implantation equipment

A typical ion implanter has five main subsystems, each handling a different stage of the process:

Ion source generates ions of the desired dopant species (e.g., boron, phosphorus, arsenic)
Mass analyzer uses a magnetic field to filter ions by charge-to-mass ratio, selecting only the correct dopant isotope
Acceleration column applies high voltage to bring ions up to the target energy
Beam scanning system deflects the beam to ensure uniform coverage across the entire wafer surface
End station handles wafer loading, alignment, and cooling during implantation

Ion beam generation

Plasma-based ion sources (Bernas, Freeman, inductively coupled plasma) ionize dopant atoms through collisions with energetic electrons in a plasma discharge. These are the most common sources in production implanters.
Solid-state ion sources (sputtering, thermal ionization) produce ions directly from a solid material containing the dopant. These are used for species that are difficult to generate from gas-phase precursors.

Ion acceleration and focusing

Electrostatic acceleration uses high-voltage electrodes to bring ions to the desired energy
Magnetic focusing shapes the beam cross-section and improves uniformity at the wafer
Electrostatic deflection scans the beam across the wafer surface for even dose delivery

Wafer handling in ion implantation

The wafer is loaded into the end station and aligned relative to the ion beam
Electrostatic clamping holds the wafer securely during implantation
A cooling system (typically gas-assisted backside cooling) keeps the wafer temperature low enough to prevent unintended diffusion or photoresist damage

Dose control in ion implantation

Accurate dose control is what makes implantation so reproducible:

A Faraday cup measures the ion beam current reaching the wafer
Integrating that current over time gives the total implanted dose (ions/cm²)
A feedback loop adjusts beam current or scan speed to maintain the target dose rate

Energy control in ion implantation

The acceleration voltage directly sets the ion energy
Higher energy means deeper dopant penetration into the substrate
For very shallow implants (below ~10 keV), a deceleration mode is used where ions are first accelerated and then slowed down, which provides better beam quality at low energies

Ion implantation parameters

Choosing the right implantation parameters determines the final dopant profile and the electrical characteristics of your device. The four key parameters are ion species, dose, energy, and tilt/twist angles.

Ion species selection

The dopant type (n-type or p-type) dictates the species
Common n-type dopants: phosphorus (P), arsenic (As), antimony (Sb)
Common p-type dopants: boron (B), indium (In), gallium (Ga)
Species choice also affects diffusion behavior during subsequent annealing. For example, arsenic diffuses much more slowly than phosphorus in silicon, so As is preferred for shallow n-type junctions.

Implantation dose

Dose is the total number of dopant atoms introduced per unit area, typically expressed in atoms/cm² (e.g., $1 \times 10^{15}$ cm $^{-2}$ )
Higher doses produce higher peak dopant concentrations
Dose uniformity across the wafer is critical; even small variations can shift threshold voltages and degrade yield

Implantation energy

Energy determines how deep dopants penetrate into the substrate, expressed in eV or keV
Higher energies produce deeper profiles. For example, a 100 keV boron implant into silicon has a projected range of roughly 300 nm, while a 10 keV implant reaches only about 35 nm.
Energy is selected based on the target junction depth and the desired shape of the dopant distribution

Tilt and twist angles

Tilt angle: the angle between the ion beam and the wafer surface normal. A non-zero tilt (typically 7°) is used to avoid channeling, where ions travel deep along crystal axes.
Twist angle: rotation of the wafer about its surface normal. This improves dopant uniformity and reduces shadowing from surface topography.
Typical tilt angles range from 0° to 30°; twist angles are often set to 0° or 45°.

Ion stopping and range

When an implanted ion enters the substrate, it loses energy through collisions until it comes to rest. The way it loses energy determines both the final dopant depth and the amount of crystal damage left behind.

Nuclear stopping

Elastic collisions between the incoming ion and target atom nuclei
Dominant at low ion energies (below ~10 keV for light ions)
Each collision can knock a target atom off its lattice site, causing significant lattice damage and displacement cascades
Responsible for defect formation and, at high doses, amorphization of the substrate

Electronic stopping

Inelastic interactions between the incoming ion and the electron cloud of target atoms
Dominant at high ion energies (above ~100 keV)
Energy is lost through ionization and excitation of target electrons
Causes less structural damage than nuclear stopping because the lattice atoms themselves aren't displaced

Projected range and straggle

Projected range ( $R_p$ ): the average depth at which implanted ions come to rest
Straggle ( $\Delta R_p$ ): the standard deviation of the depth distribution, describing how spread out the profile is around $R_p$
Both depend on the ion species, implantation energy, and target material
Can be estimated using LSS theory (Lindhard, Scharff, Schiøtt) or calculated more accurately with Monte Carlo simulations

Channeling effects

Channeling occurs when the ion beam aligns with a major crystallographic direction of the substrate (e.g., the <110> axis in silicon). Ions traveling down these open "channels" experience reduced stopping and penetrate much deeper than expected, creating a long tail on the dopant profile.

Tilting the wafer by ~7° off-axis is the standard way to minimize channeling. Pre-amorphization implants (e.g., silicon or germanium) can also eliminate channels by destroying the crystal order before the dopant implant.

Monte Carlo simulation of ion stopping

A numerical method that simulates individual ion trajectories and their random collision sequences in the target
Accounts for the stochastic (random) nature of each ion-atom interaction
Produces detailed predictions of the dopant depth distribution and the spatial distribution of lattice damage
Tools like SRIM/TRIM and Crystal-TRIM are widely used for this purpose

Damage and annealing

Ion implantation inevitably damages the crystal lattice. Post-implantation annealing is required to repair this damage, activate dopants onto substitutional lattice sites, and control the final dopant distribution.

Lattice damage during implantation

Energetic ions knock target atoms off their lattice sites, creating point defects: vacancies (missing atoms) and interstitials (extra atoms between lattice sites)
At higher doses, point defects cluster into extended defects like dislocation loops
The damage profile roughly follows the ion energy deposition profile, peaking near $R_p$
Damage severity depends on ion species (heavier ions cause more damage), energy, and dose

Amorphization and recrystallization

Above a critical dose, damage accumulates to the point where the implanted layer becomes amorphous, losing all long-range crystal order
During annealing, this amorphous layer recrystallizes through solid-phase epitaxial regrowth (SPER), which proceeds from the underlying crystalline substrate upward
SPER is fast and produces high-quality crystal, but end-of-range (EOR) defects (dislocation loops) often form at the original amorphous/crystalline interface and can be difficult to fully eliminate

Thermal annealing processes

Three main annealing approaches are used, each trading off between damage repair and dopant redistribution:

Furnace annealing: minutes to hours at 500–1000°C. Good for damage repair but causes significant dopant diffusion.
Rapid thermal annealing (RTA): seconds at 1000–1200°C. Activates dopants with much less diffusion, better for maintaining shallow junctions.
Spike annealing: milliseconds at peak temperatures of 1200–1300°C. Minimizes the thermal budget even further, keeping profiles nearly as-implanted.

Rapid thermal annealing (RTA)

RTA uses high-intensity lamps (tungsten-halogen or xenon arc) to heat the wafer rapidly:

Ramp rates of 50–200°C/s
Temperature is monitored in real time using pyrometry or thermocouple feedback
The short time at peak temperature activates dopants while limiting diffusion
This makes RTA the standard anneal for forming shallow, highly activated junctions in modern CMOS processes

Laser annealing

Uses pulsed laser irradiation (typically excimer lasers, nanosecond pulses) to melt and recrystallize just the surface layer
Heating is extremely localized and brief, so dopant diffusion is negligible
Can achieve very high dopant activation, even above the equilibrium solid solubility (supersaturation)
Increasingly used for ultra-shallow junction formation in advanced technology nodes

Defects after annealing

Even after annealing, residual defects can affect device performance:

End-of-range (EOR) defects: dislocation loops at the former amorphous/crystalline boundary that persist even after high-temperature anneals
Transient enhanced diffusion (TED): excess interstitials released during annealing temporarily boost dopant diffusion rates far above equilibrium values, broadening the profile
Dopant deactivation: at high concentrations, dopants can form inactive clusters or precipitates, reducing the electrically active fraction

Diffusion in semiconductors

Diffusion is the thermally driven movement of atoms from regions of high concentration to low concentration. In semiconductor fabrication, it governs how dopant profiles evolve during any high-temperature step, not just intentional diffusion processes but also during oxidation, annealing, and deposition.

Fick's laws of diffusion

Fick's first law relates the flux of diffusing atoms to the concentration gradient:

$J = -D \frac{\partial C}{\partial x}$

where $J$ is the diffusive flux (atoms/cm²·s), $D$ is the diffusion coefficient (cm²/s), and $C$ is the dopant concentration. The negative sign means atoms flow from high to low concentration.

Fick's second law describes how the concentration profile changes over time:

$\frac{\partial C}{\partial t} = D \frac{\partial^2 C}{\partial x^2}$

This holds when $D$ is constant (independent of concentration and position). Solving this equation with appropriate boundary conditions gives you the dopant profile after diffusion.

Diffusion mechanisms

Dopant atoms in semiconductors don't just slide through the lattice on their own. They move by interacting with point defects:

A dopant atom can swap positions with a neighboring vacancy
A dopant atom can be kicked off its lattice site by a self-interstitial and migrate through interstitial sites

The dominant mechanism depends on the dopant species, its concentration, and the temperature. Most common substitutional dopants in silicon (B, P, As) diffuse through a combination of both mechanisms.

Interstitial diffusion

The diffusing atom occupies interstitial sites (spaces between lattice atoms) and hops from one interstitial site to the next
Typically much faster than vacancy diffusion because the activation energy barrier is lower
Common for small atoms like hydrogen (H), lithium (Li), and sodium (Na), as well as fast-diffusing transition metals like copper (Cu), nickel (Ni), and iron (Fe)
These fast diffusers are usually contaminants you want to keep out of the active device region

Vacancy diffusion

The dopant atom moves by exchanging positions with a neighboring vacancy in the lattice
Requires vacancies to be present, either at their thermal equilibrium concentration or in excess (e.g., after implantation)
This is the primary mechanism for substitutional dopants like B, P, As, and Sb in silicon

Diffusion coefficients and activation energy

The diffusion coefficient $D$ follows an Arrhenius relationship:

$D = D_0 \exp\left(\frac{-E_a}{kT}\right)$

$D_0$ is the pre-exponential factor (cm²/s)
$E_a$ is the activation energy (eV), representing the energy barrier for atomic migration
$k$ is Boltzmann's constant ( $8.617 \times 10^{-5}$ eV/K)
$T$ is the absolute temperature (K)

Each dopant-substrate combination has its own $D_0$ and $E_a$ . For example, boron in silicon has $E_a \approx 3.46$ eV, while arsenic has $E_a \approx 4.05$ eV, which is why arsenic diffuses more slowly at any given temperature.

Temperature dependence of diffusion

Because of the exponential in the Arrhenius equation, even small temperature changes cause large changes in diffusion rate. A 50°C increase can roughly double or triple the diffusion coefficient. This is why precise temperature control during annealing and other thermal steps is so critical for maintaining the intended dopant profiles.

Diffusion profiles

The shape of the dopant concentration vs. depth curve after diffusion depends on the boundary conditions, specifically whether the dopant supply at the surface is limited or constant.

Gaussian diffusion profile

When a fixed total amount of dopant $Q$ (atoms/cm²) is placed at or near the surface and then diffused, the resulting profile is Gaussian:

$C(x,t) = \frac{Q}{\sqrt{4\pi Dt}} \exp\left(\frac{-x^2}{4Dt}\right)$

The peak concentration is at the surface and decreases with time as dopant spreads deeper. This is sometimes called a "drive-in" diffusion, where no additional dopant is supplied during the thermal step.

Complementary error function (erfc) profile

When the surface concentration $C_s$ is held constant throughout the diffusion (e.g., by a gas-phase dopant source), the profile follows the complementary error function:

$C(x,t) = C_s \, \mathrm{erfc}\left(\frac{x}{2\sqrt{Dt}}\right)$

This produces a steeper near-surface profile compared to the Gaussian case. The surface concentration stays fixed while dopant penetrates progressively deeper with time.

Finite and infinite source diffusion

Finite source (drive-in): A limited amount of dopant is available (e.g., from a thin deposited layer or a previous implant). The surface concentration drops over time as dopant redistributes. Produces a Gaussian profile.

Infinite source (predeposition): A constant supply of dopant maintains a fixed surface concentration throughout the process (e.g., from a gas-phase source). Produces an erfc profile.

Many real processes use a two-step approach: first a predeposition (erfc) to introduce dopant, then a drive-in (Gaussian-like) to push it deeper and shape the junction.

Diffusion in multiple dimensions

Real devices have 2D and 3D geometries, so dopant diffusion doesn't just go straight down. The full 3D diffusion equation is:

$\frac{\partial C}{\partial t} = D \left(\frac{\partial^2 C}{\partial x^2} + \frac{\partial^2 C}{\partial y^2} + \frac{\partial^2 C}{\partial z^2}\right)$

Lateral diffusion under mask edges, interactions with oxide interfaces, and non-planar device structures all create complex profiles that require numerical methods (finite difference or finite element) to solve accurately.

Process simulation

Process simulation tools let you model the entire fabrication sequence virtually, predicting dopant profiles, material structures, and device geometry without running expensive wafer experiments. They're essential for process development and optimization.

Process simulation tools

TCAD platforms like Sentaurus Process (Synopsys), Silvaco Athena, and TSUPREM-4 are industry standards
They integrate models for implantation, diffusion, oxidation, etching, deposition, and other process steps into a single simulation flow
You define the process sequence (temperatures, times, doses, energies) and the tool calculates the resulting 1D, 2D, or 3D dopant and material profiles

Implantation and diffusion models

These tools offer multiple levels of model fidelity:

Analytical models (LSS theory, Gaussian, dual-Pearson): fast to compute but limited in accuracy, especially for channeling tails or complex target structures
Monte Carlo models (Binary Collision Approximation, Crystal-TRIM): simulate individual ion trajectories stochastically, giving detailed stopping and damage distributions at higher computational cost
Diffusion models (Fick's laws, pair diffusion, TED models): describe how profiles evolve during thermal steps, accounting for defect-mediated diffusion and the temperature dependence of diffusion coefficients

Calibration and verification of models

Simulation models contain adjustable parameters that must be calibrated against experimental measurements to produce trustworthy predictions:

Secondary Ion Mass Spectrometry (SIMS) measures the chemical dopant concentration vs. depth
Spreading Resistance Profiling (SRP) measures the electrically active carrier concentration vs. depth
Transmission Electron Microscopy (TEM) reveals structural defects and layer thicknesses

Calibration is iterative: you compare simulation output to experimental data, adjust model parameters, and repeat until the agreement is satisfactory across a range of process conditions.

Applications of ion implantation and diffusion

These two processes appear in nearly every step of modern semiconductor device fabrication, from setting background doping levels to fine-tuning transistor characteristics.

Doping of semiconductors

Ion implantation introduces dopants to control whether a region is n-type or p-type and to set the carrier concentration. Unlike blanket diffusion from a gas source, implantation through a patterned mask allows localized doping, creating the complex spatial dopant profiles that modern devices require.

Junction formation

Shallow junctions (e.g., source/drain extensions in advanced CMOS): formed by low-energy implantation followed by RTA or spike annealing to minimize diffusion and maintain abrupt profiles. Critical for scaling device dimensions below 100 nm.
Deep junctions (e.g., well implants, power device structures): formed using high-energy implantation or extended thermal diffusion. These provide isolation between devices or handle high voltages in power electronics.

Threshold voltage adjustment

The threshold voltage ( $V_{th}$ ) of a MOSFET depends on the doping concentration in the channel region. Ion implantation is used to precisely adjust $V_{th}$ through:

Channel implants that set the baseline doping under the gate
Pocket (halo) implants that suppress short-channel effects by increasing doping near the source/drain edges

These implants allow designers to optimize the tradeoff between performance, leakage current, and power consumption.

Source/drain engineering

Forming high-quality source and drain regions involves multiple implant and diffusion steps:

Lightly doped drain (LDD) structures use a lower-dose implant before spacer formation to reduce the peak electric field at the drain edge, suppressing hot carrier degradation
Deep source/drain implants after spacer formation provide low-resistance contact regions
Elevated source/drain and selective epitaxial growth (SEG) techniques reduce parasitic resistance and can introduce strain for enhanced carrier mobility

Gettering of impurities

Ion implantation can also serve a non-doping purpose: creating gettering sites that trap unwanted metallic contaminants (Cu, Fe, Ni) away from the active device region.

Phosphorus or argon is implanted into the wafer backside
The implantation damage creates a high density of trapping sites
During subsequent thermal steps, mobile metal impurities migrate to these sites and are immobilized
This improves device yield and reliability by keeping the front-side active region clean

2,589 studying →