8.1 MOSFET structure and operation

MOSFETs are the workhorses of modern electronics, controlling current flow in everything from smartphone processors to power converters. Understanding their structure and operation is foundational to semiconductor physics and circuit design.

This topic covers MOSFET device structure, operation principles, operating modes, and their use as switches and amplifiers. It also addresses advanced concepts like channel length modulation and the challenges that arise as devices are scaled to smaller dimensions.

MOSFET device structure

A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is built from several distinct layers and regions, each playing a specific role. The name itself tells you the stack: a metal (or polysilicon) gate, an oxide insulator, and a semiconductor substrate.

Semiconductor substrate

The substrate is a lightly doped silicon ($Si$) crystal that forms the physical foundation of the device. It can be p-type (majority carriers are holes) or n-type (majority carriers are electrons), and this choice determines whether you're building an n-channel or p-channel MOSFET. Beyond providing mechanical support, the substrate's doping level directly influences the threshold voltage and other electrical characteristics.

Source and drain regions

These are heavily doped regions implanted into the substrate with the opposite doping type. For an n-channel MOSFET on a p-type substrate, the source and drain are n+ regions. The source supplies charge carriers (electrons in an nMOS) that travel through the channel and are collected at the drain. Structurally, the source and drain are symmetric, but they're distinguished by the voltage applied to them during operation.

Gate electrode

The gate is a conductive layer, typically heavily doped polysilicon or metal, positioned directly above the channel region. It does not carry the main device current. Instead, the voltage applied to the gate creates an electric field that controls whether a conductive channel forms between source and drain. Think of it as one plate of a parallel-plate capacitor, with the gate oxide as the dielectric.

Gate oxide layer

A thin insulating film of silicon dioxide ($SiO_2$), sitting between the gate electrode and the substrate surface. This layer is critical: it blocks DC current from flowing between the gate and the channel while allowing the gate's electric field to penetrate into the substrate and modulate the carrier concentration. The oxide's thickness and quality directly affect device performance, reliability, and leakage. In modern technology nodes, this layer can be just a few nanometers thick.

Body terminal

Some MOSFET configurations provide access to a fourth terminal connected to the substrate (also called the body or bulk). Applying a bias voltage to the body modulates the threshold voltage through the body effect. In most integrated circuits, the body is tied to the source or to a fixed supply rail ($V_{DD}$ or ground) to simplify operation.

MOSFET operation principles

MOSFETs use the field effect to control current: a voltage on the gate creates an electric field that attracts or repels carriers in the substrate, forming or eliminating a conductive path between source and drain. No gate current is needed to maintain this control, which is why MOSFETs have extremely high input impedance.

Applying gate voltage

When you apply a voltage to the gate, an electric field develops across the gate oxide and into the substrate beneath it. This field redistributes charge carriers near the substrate surface. In an nMOS device on a p-type substrate, a positive gate voltage repels holes away from the surface and attracts electrons toward it.

Forming the conductive channel

• n-channel MOSFET: A sufficiently positive gate voltage attracts enough electrons to the substrate surface to invert the surface from p-type to n-type, creating a thin conducting channel that connects source to drain.
• p-channel MOSFET: A sufficiently negative gate voltage drives electrons away and attracts holes, forming a p-type channel on an n-type substrate.

The channel's conductivity scales with the magnitude of the gate voltage above threshold, giving you continuous control over current flow.

Controlling drain current

The drain current ($I_D$) depends on two voltages: the gate-to-source voltage ($V_{GS}$) and the drain-to-source voltage ($V_{DS}$). Once $V_{GS}$ exceeds the threshold voltage, a channel exists, and applying $V_{DS}$ drives current through it. Increasing $V_{GS}$ further deepens the channel (more carriers), increasing the current.

Threshold voltage concept

The threshold voltage ($V_T$) is the minimum gate-to-source voltage needed to create an inversion layer and form a conducting channel. Below $V_T$, the device is essentially off (cut-off). Above $V_T$, the device turns on and conducts.

$V_T$ depends on several factors:

• Substrate doping concentration (higher doping raises $V_T$)
• Gate oxide thickness (thicker oxide raises $V_T$)
• Oxide charges and work function difference between gate and substrate

Transconductance parameter

Transconductance ($g_m$) quantifies how effectively the gate voltage controls the drain current. It's defined as:

$g_m = \frac{\partial I_D}{\partial V_{GS}}$

A higher $g_m$ means a small change in gate voltage produces a large change in drain current. This is the key parameter for amplifier design: it determines voltage gain. Transconductance increases with wider channels, thinner gate oxides, higher carrier mobility, and larger bias currents.

MOSFET operating modes

Depending on the relationship between $V_{GS}$, $V_T$, and $V_{DS}$, a MOSFET operates in one of three distinct modes. Recognizing which mode applies is essential for circuit analysis.

Cut-off mode

When $V_{GS} < V_T$, no inversion layer forms. The channel doesn't exist, so ideally $I_D = 0$. The device behaves as an open switch. In practice, a small subthreshold leakage current still flows, but it's negligible for most applications.

Linear vs. saturation mode

Once $V_{GS} > V_T$, the device is on, and the operating mode depends on $V_{DS}$:

Linear (triode) mode: $V_{DS} < V_{GS} - V_T$

• The channel extends continuously from source to drain.
• The MOSFET behaves like a voltage-controlled resistor.
• Drain current depends on both $V_{GS}$ and $V_{DS}$.

Saturation mode: $V_{DS} \geq V_{GS} - V_T$

• The channel is pinched off near the drain end.
• Drain current becomes nearly independent of $V_{DS}$ and is controlled primarily by $V_{GS}$.
• The device acts like a voltage-controlled current source.

The boundary between these two regions occurs at $V_{DS} = V_{GS} - V_T$, called the pinch-off condition.

Deriving current equations

Using the gradual channel approximation, the drain current equations are:

Linear mode:

$I_D = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_T)V_{DS} - \frac{1}{2}V_{DS}^2\right]$

Saturation mode:

$I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2$

Where:

• $\mu_n$ = electron mobility in the channel
• $C_{ox}$ = gate oxide capacitance per unit area
• $W$ = channel width, $L$ = channel length
• The ratio $W/L$ is a key design parameter that sets the device's current-driving capability

The product $\mu_n C_{ox}$ is often called the process transconductance parameter ($k'_n$), and $\frac{1}{2} k'_n \frac{W}{L}$ is sometimes written as $K_n$.

Output characteristics

The output characteristics plot $I_D$ vs. $V_{DS}$ for several fixed values of $V_{GS}$. Each curve shows the linear region (where current rises with $V_{DS}$), the transition at pinch-off, and the saturation region (where current levels off). These curves are essential for determining the operating point of a MOSFET in a circuit.

Transfer characteristics

The transfer characteristics plot $I_D$ vs. $V_{GS}$ at a fixed $V_{DS}$. You can read $V_T$ from where the curve departs from zero (or from the x-axis intercept of the extrapolated linear portion in saturation). The slope of this curve in saturation gives you the transconductance $g_m$.

MOSFET as switch vs. amplifier

The same MOSFET can serve as a switch or an amplifier depending on which operating regions you use and how you design the surrounding circuit.

Switch-mode operation

For switching, the MOSFET toggles between cut-off (off, high resistance) and the linear region (on, low resistance). The transition should be as fast as possible. Digital logic gates, power converters, and motor drivers all rely on MOSFETs operating this way. The key performance metrics are on-resistance ($R_{on}$), switching speed, and power dissipation during transitions.

Amplifier-mode operation

For amplification, the MOSFET is biased in the saturation region at a stable DC operating point (the Q-point). Small AC signals on the gate produce proportionally larger AC variations in the drain current. The voltage gain of a common-source amplifier, for example, is proportional to $g_m$ multiplied by the load resistance. Analog circuits like op-amps, RF amplifiers, and sensor front-ends use MOSFETs in this mode.

Small-signal model

Around the DC operating point, the MOSFET's nonlinear behavior can be linearized into a small-signal equivalent circuit. The core element is a voltage-controlled current source ($g_m v_{gs}$) from drain to source. Additional components include:

• $r_o$: output resistance (due to channel length modulation), equal to $1/(\lambda I_D)$
• $C_{gs}$, $C_{gd}$: parasitic capacitances between gate-source and gate-drain

This model is the starting point for calculating gain, input/output impedance, and bandwidth of amplifier circuits.

Frequency response

MOSFET amplifiers have parasitic capacitances ($C_{gs}$, $C_{gd}$, $C_{db}$) that create poles in the frequency response, limiting high-frequency gain. Two important figures of merit:

• Unity-gain frequency ($f_T$): the frequency where the current gain drops to 1. It's approximately $f_T \approx \frac{g_m}{2\pi(C_{gs} + C_{gd})}$.
• Maximum oscillation frequency ($f_{max}$): the frequency where power gain drops to 1.

Higher $g_m$ and lower parasitic capacitances push these frequencies higher.

Gain-bandwidth product

The gain-bandwidth product (GBW) equals the low-frequency voltage gain multiplied by the bandwidth (the frequency at which gain drops by 3 dB). For a given MOSFET technology, GBW is roughly constant: if you increase gain, bandwidth decreases, and vice versa. GBW is set by the intrinsic device parameters, primarily $g_m$ and the parasitic capacitances.

Advanced MOSFET concepts

As channel lengths shrink into the nanometer range, several second-order effects become significant enough to affect device behavior and circuit performance.

Channel length modulation

In saturation, the pinch-off point moves slightly toward the source as $V_{DS}$ increases, effectively shortening the channel. This means $I_D$ isn't truly constant in saturation but increases slightly with $V_{DS}$. The modified saturation current equation accounts for this:

$I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_T)^2 (1 + \lambda V_{DS})$

where $\lambda$ is the channel length modulation parameter (units of $V^{-1}$). This effect gives the MOSFET a finite output resistance $r_o = \frac{1}{\lambda I_D}$ in saturation, which matters for amplifier design.

Velocity saturation

In long-channel devices, carrier velocity increases linearly with the electric field. In short-channel devices, the field can become so high that carriers reach a maximum saturation velocity ($v_{sat} \approx 10^7$ cm/s for electrons in silicon). Once velocity saturates, the drain current no longer follows the square-law equation and instead becomes more linearly dependent on $V_{GS} - V_T$. This reduces both the maximum current and the transconductance compared to long-channel predictions.

Drain-induced barrier lowering

DIBL is a short-channel effect where a high drain voltage lowers the potential barrier at the source end of the channel. This effectively reduces the threshold voltage as $V_{DS}$ increases, causing higher off-state leakage and degraded subthreshold slope. DIBL becomes more pronounced as the channel length decreases and the drain's electric field reaches closer to the source.

Hot carrier effects

When carriers gain very high kinetic energy from the electric field (becoming "hot"), they can:

• Get injected into the gate oxide, creating trapped charge
• Generate electron-hole pairs through impact ionization
• Create interface traps at the $Si/SiO_2$ boundary

Over time, this degrades threshold voltage, transconductance, and overall reliability. Mitigation strategies include lightly doped drain (LDD) structures, which spread out the electric field near the drain, and reducing supply voltages.

Latch-up phenomenon

Latch-up is specific to CMOS circuits, where adjacent nMOS and pMOS transistors create a parasitic PNPN thyristor structure in the substrate. If triggered (by voltage spikes, radiation, or ESD events), this structure latches into a low-resistance, high-current state that can destroy the chip. Prevention techniques include:

• Guard rings around transistors to collect stray carriers
• Proper substrate and well contacts
• Adequate spacing between n-well and p-well regions
• Epitaxial substrates with low-resistance bulk

MOSFET scaling and limitations

Scaling means shrinking MOSFET dimensions to fit more transistors on a chip, increase speed, and reduce power per device. But scaling doesn't come for free.

Scaling laws and constants

Dennard scaling (constant-field scaling) prescribes that when all dimensions are reduced by a factor $\alpha$, voltages should also scale by $\alpha$ to keep the electric field constant. Under ideal Dennard scaling:

• Gate delay decreases by $\alpha$
• Power per device decreases by $\alpha^2$
• Power density stays constant

In practice, Dennard scaling broke down around the 90 nm node because threshold voltage and supply voltage couldn't keep scaling without unacceptable leakage increases.

Short-channel effects

When the channel length approaches the same order as the source/drain depletion widths, the gate loses some control over the channel. Short-channel effects include:

• Threshold voltage roll-off: $V_T$ decreases as $L$ shrinks
• DIBL: drain voltage influences the source barrier
• Subthreshold slope degradation: the device can't turn off as sharply
• Increased leakage current: higher off-state power consumption

Advanced device architectures like FinFETs (multi-gate transistors) and gate-all-around (GAA) structures improve gate control and suppress these effects.

Gate leakage current

As the gate oxide thins below about 2 nm of $SiO_2$, quantum mechanical tunneling allows carriers to pass directly through the oxide. Gate leakage increases exponentially with decreasing oxide thickness, adding to standby power and reducing reliability. The solution is to replace $SiO_2$ with high-k dielectrics that provide the same capacitance with a physically thicker (and therefore less leaky) film.

Oxide breakdown

If the electric field across the gate oxide exceeds a critical value, the oxide suffers irreversible breakdown. This can happen suddenly (hard breakdown) or gradually through progressive defect accumulation (soft breakdown). Oxide breakdown sets an upper limit on the operating voltage for a given oxide thickness. Better manufacturing processes and careful design margins help ensure reliability over the device's lifetime.

Alternative gate dielectrics

Conventional $SiO_2$ has a dielectric constant ($k$) of about 3.9. High-k materials have much larger dielectric constants:

• Hafnium oxide ($HfO_2$): $k \approx 25$
• Zirconium oxide ($ZrO_2$): $k \approx 25$
• Aluminum oxide ($Al_2O_3$): $k \approx 9$

A higher $k$ means you can use a physically thicker film while achieving the same (or better) gate capacitance, dramatically reducing tunneling leakage. The combination of high-k dielectrics with metal gates (replacing polysilicon) has been standard in advanced CMOS technology since the 45 nm node.