7.2 Flat-band voltage and threshold voltage

Flat-band voltage

Flat-band voltage is one of the key reference points for understanding how an MOS capacitor responds to applied bias. It tells you the gate voltage needed to make the energy bands in the semiconductor perfectly flat, meaning there's no bending, no accumulation, and no depletion at the surface.

Definition of flat-band voltage

The flat-band voltage ($V_{FB}$) is the gate voltage that produces zero electric field in the oxide and zero surface potential in the semiconductor. In other words, the energy band diagram looks completely flat from the bulk all the way to the surface.

Two things primarily set the value of $V_{FB}$:

• The work function difference between the gate material and the semiconductor
• Any fixed charges trapped in the oxide or at the interface

If there were no charges in the oxide and the gate and semiconductor had identical work functions, $V_{FB}$ would simply be zero. In real devices, it almost never is.

Factors affecting flat-band voltage

• Work function difference ($\Phi_{MS}$): This is the difference between the gate metal work function and the semiconductor work function, $\Phi_{MS} = \Phi_M - \Phi_S$. A larger mismatch means a larger built-in voltage that must be compensated.
• Fixed oxide charges ($Q_f$): These are charges embedded in the oxide during fabrication. Positive fixed charges push $V_{FB}$ more negative, because you need a more negative gate voltage to counteract their effect. Negative fixed charges do the opposite.
• Interface trap charges ($Q_{it}$): Charges at the oxide-semiconductor interface that can also shift $V_{FB}$, though their contribution depends on the Fermi level position.
• Oxide capacitance ($C_{ox}$): Determined by the oxide thickness ($t_{ox}$) and permittivity ($\varepsilon_{ox}$). A thinner oxide means larger $C_{ox}$, so the same amount of trapped charge produces a smaller voltage shift.

Flat-band voltage equation

The flat-band condition corresponds to zero surface potential ($\psi_s = 0$). The standard expression is:

$V_{FB} = \Phi_{MS} - \frac{Q_f + Q_{it}}{C_{ox}}$

where $C_{ox} = \varepsilon_{ox} / t_{ox}$ is the oxide capacitance per unit area.

This equation makes physical sense: you start with the work function mismatch, then correct for any charges sitting in the oxide that create additional band bending you need to undo.

Methods for determining flat-band voltage

• Capacitance-Voltage (C-V) measurements: The most common approach. You sweep the gate voltage and measure the capacitance. The flat-band capacitance $C_{FB}$ is calculated from the known doping and oxide thickness, and the voltage at which the measured capacitance equals $C_{FB}$ gives you $V_{FB}$.
• Charge-Based Capacitance Measurement (CBCM): Determines $V_{FB}$ by tracking how charge in the semiconductor varies with applied voltage. Useful for thin-oxide devices where standard C-V can be complicated by tunneling currents.
• Kelvin Probe Force Microscopy (KPFM): Measures the surface potential and work function directly, from which $V_{FB}$ can be derived. More of a research tool than a production technique.

Threshold voltage

While flat-band voltage tells you when the bands are flat, threshold voltage tells you when the device actually turns on. For a MOSFET, this is the gate voltage at which a conducting inversion layer forms between source and drain.

Definition of threshold voltage

The threshold voltage ($V_{th}$) is the gate voltage at which the surface of the semiconductor reaches strong inversion. Formally, strong inversion occurs when the surface potential equals twice the bulk potential: $\psi_s = 2\psi_B$.

• For an n-channel MOSFET (p-type substrate), $V_{th}$ is the gate voltage that attracts enough electrons to the surface to form an n-type inversion layer.
• For a p-channel MOSFET (n-type substrate), $V_{th}$ is the gate voltage that attracts enough holes to form a p-type inversion layer.

Below $V_{th}$, the transistor is in its off-state (subthreshold region). Above $V_{th}$, current flows freely through the channel.

Factors influencing threshold voltage

• Flat-band voltage ($V_{FB}$): Since $V_{th}$ builds on top of $V_{FB}$, anything that shifts $V_{FB}$ also shifts $V_{th}$.
• Substrate doping concentration ($N_A$ or $N_D$): Higher doping means more depletion charge must be supported, which raises $V_{th}$.
• Oxide thickness ($t_{ox}$): Thinner oxides give stronger gate-to-channel coupling (larger $C_{ox}$), which lowers $V_{th}$.
• Work function difference ($\Phi_{MS}$): Affects $V_{th}$ through its effect on $V_{FB}$.
• Oxide and interface charges ($Q_f$, $Q_{it}$): Same mechanism as their effect on $V_{FB}$.

Threshold voltage equation

For an n-channel device on a p-type substrate:

$V_{th} = V_{FB} + 2\psi_B + \frac{\sqrt{4\varepsilon_{si}qN_A\psi_B}}{C_{ox}}$

where:

• $\psi_B = \frac{kT}{q}\ln\left(\frac{N_A}{n_i}\right)$ is the bulk potential
• $\varepsilon_{si}$ is the permittivity of silicon
• $q$ is the elementary charge
• $N_A$ is the acceptor doping concentration

The three terms have clear physical meaning:

1. $V_{FB}$ compensates for the work function mismatch and oxide charges
2. $2\psi_B$ is the voltage needed to bend the bands enough for strong inversion
3. The third term accounts for the depletion charge that must be supported by the gate

$V_{th}$ is always larger in magnitude than $V_{FB}$ because of the additional voltage needed to create the inversion layer.

Body effect on threshold voltage

When a voltage is applied between the source and the substrate (body), the threshold voltage changes. This is called the body effect.

Applying a reverse bias $V_{SB}$ to the substrate widens the depletion region, increasing the depletion charge. The gate then needs a higher voltage to reach inversion. The modified threshold voltage is:

$V_{th} = V_{th0} + \gamma\left(\sqrt{2\psi_B + V_{SB}} - \sqrt{2\psi_B}\right)$

where $V_{th0}$ is the threshold voltage at zero body bias, and $\gamma$ is the body effect coefficient:

$\gamma = \frac{\sqrt{2\varepsilon_{si}qN_A}}{C_{ox}}$

The body effect matters in circuits where the source is not tied to the substrate, such as stacked transistors in NMOS logic or series-connected devices in SRAM cells.

Methods for extracting threshold voltage

• Linear Extrapolation Method (LEM): Plot $I_D$ vs. $V_{GS}$ in the linear region. Fit a straight line to the steepest part and extrapolate to $I_D = 0$. The x-intercept gives $V_{th}$.
• Constant Current Method (CCM): Define $V_{th}$ as the gate voltage where the drain current reaches a fixed value (commonly $I_D = 0.1\ \mu A \times W/L$). Simple and widely used in industry.
• Transconductance Method (GM): Find the peak of the transconductance $g_m = dI_D/dV_{GS}$ curve. The gate voltage at the peak (or its extrapolation) corresponds to $V_{th}$.
• Subthreshold Slope Method: Extract $V_{th}$ from the log-scale $I_D$-$V_{GS}$ plot in the subthreshold region by identifying where the current transitions from exponential to linear dependence.

Each method gives a slightly different value, so it's important to specify which method was used when reporting $V_{th}$.

Importance in semiconductor devices

Role of flat-band and threshold voltages

$V_{FB}$ serves as the reference point for the MOS system. It tells you where the "zero" is on the band diagram, and every other operating regime (accumulation, depletion, inversion) is defined relative to it.

$V_{th}$ determines the boundary between the off-state and on-state of a MOSFET. This single parameter controls:

• Whether the transistor conducts or blocks current
• The noise margins in digital logic
• The static power dissipation of a circuit

Impact on device performance

Shifts in $V_{FB}$ distort the C-V characteristics of MOS capacitors, which can throw off circuit timing and analog signal processing.

$V_{th}$ directly affects several critical MOSFET parameters:

• On-state current ($I_{on}$) and off-state current ($I_{off}$): A higher $V_{th}$ reduces $I_{on}$ (slower switching) but also reduces $I_{off}$ (lower leakage power). This is the fundamental speed-vs-power trade-off.
• Subthreshold slope and leakage: $V_{th}$ sets how much gate voltage margin exists between the off-state and the noise floor. Lower $V_{th}$ means more leakage in standby.
• Short-channel effects: Drain-induced barrier lowering (DIBL) effectively reduces $V_{th}$ in short-channel devices, making threshold voltage control harder as transistors scale down.

Applications beyond MOSFETs

Flat-band and threshold voltages are also relevant in:

• MOS capacitors used in sensing and energy storage
• Charge-coupled devices (CCDs) for image sensors, where precise voltage control determines charge transfer efficiency
• Floating-gate devices (EEPROM, flash memory), where stored charge on the floating gate shifts $V_{th}$ to represent data as "0" or "1"

Techniques for controlling voltages

Doping concentration and type

• Increasing substrate doping ($N_A$ for p-type) raises $V_{th}$ because the depletion charge term grows. Decreasing it lowers $V_{th}$.
• Channel implants (also called threshold-adjust implants) add a thin, precisely controlled layer of dopants near the surface to fine-tune $V_{th}$ without changing the bulk doping. This is the most common production technique for setting $V_{th}$.
• The choice of substrate type (p-type for NMOS, n-type for PMOS) determines the polarity of $V_{th}$.

Gate material selection

The gate work function ($\Phi_M$) directly shifts $V_{FB}$ and therefore $V_{th}$.

• Higher work function metals (e.g., platinum, nickel) increase $V_{th}$ for n-channel devices.
• Lower work function metals (e.g., aluminum, titanium) reduce $V_{th}$ for p-channel devices.
• Traditional polysilicon gates have work functions that depend on their doping, giving some flexibility.
• Modern CMOS uses dual-metal gate technology: different gate metals for NMOS and PMOS transistors, allowing independent $V_{th}$ optimization for each type.

Oxide thickness optimization

• Thinner gate oxides increase $C_{ox}$, which reduces $V_{th}$ and strengthens gate control over the channel.
• However, very thin $SiO_2$ layers (below ~1.5 nm) suffer from excessive quantum-mechanical tunneling, causing unacceptable gate leakage.
• High-k dielectrics (e.g., $HfO_2$, $Al_2O_3$) solve this by providing a physically thicker film that still has a high capacitance. The equivalent oxide thickness (EOT) can be kept small while the actual film is thick enough to block tunneling.

Substrate biasing techniques

• Reverse body bias (positive $V_{SB}$ for NMOS) increases $V_{th}$, useful for reducing leakage in standby mode.
• Forward body bias (negative $V_{SB}$ for NMOS) decreases $V_{th}$, useful for boosting speed during active operation.
• Adaptive body biasing circuits dynamically adjust the substrate voltage based on operating conditions, trading off leakage and performance in real time. This is commonly used in low-power mobile processors.

Challenges and limitations

Process variations and non-uniformity

Fabrication is never perfectly uniform. Small variations in doping concentration, oxide thickness, and gate dimensions cause $V_{FB}$ and $V_{th}$ to vary from device to device, even on the same wafer.

Random dopant fluctuations (RDF) are especially problematic at small dimensions. In a modern transistor with a channel area of only a few thousand square nanometers, the actual number of dopant atoms in the channel might be in the tens or low hundreds. Statistical variation in that count causes meaningful $V_{th}$ scatter, which degrades circuit yield and performance consistency.

Process-induced mechanical stress and strain can further modify carrier mobility and band structure, adding another source of voltage variation.

Temperature dependence

Both $V_{FB}$ and $V_{th}$ shift with temperature:

• The semiconductor bandgap narrows as temperature rises, changing the work function difference and $V_{FB}$.
• The intrinsic carrier concentration ($n_i$) increases with temperature, which reduces $\psi_B$ and therefore lowers $V_{th}$.
• Carrier mobility also changes with temperature, affecting the current at a given gate overdrive.

These shifts mean a circuit designed at room temperature may behave differently at the extremes of its operating range (e.g., $-40°C$ to $125°C$ for automotive applications). Temperature compensation circuits or design guardbands are used to handle this.

Reliability issues

Over time, $V_{FB}$ and $V_{th}$ can drift due to:

• Charge trapping in the oxide or at the interface, which gradually shifts the voltage.
• Bias temperature instability (BTI): Under sustained gate bias at elevated temperature, interface traps and oxide charges build up, shifting $V_{th}$. Negative BTI (NBTI) in PMOS devices is particularly well-studied and remains a major reliability concern.
• Hot carrier injection (HCI): High-energy carriers near the drain can become trapped in the oxide, causing localized $V_{th}$ shifts.

Mitigation techniques include post-metallization annealing, hydrogen passivation of interface traps, and designing circuits with sufficient margin to tolerate expected drift over the product lifetime.

Trade-offs in device design

Optimizing $V_{th}$ always involves trade-offs:

• Lower $V_{th}$ gives faster switching and higher $I_{on}$, but increases standby leakage ($I_{off}$) and power consumption.
• Higher $V_{th}$ reduces leakage but slows the device down.
• Higher doping improves isolation and reduces short-channel effects, but degrades carrier mobility and increases junction capacitance.

In practice, modern chips use multi-threshold voltage (multi-$V_t$) design: critical-path transistors get low $V_{th}$ for speed, while non-critical transistors get high $V_{th}$ to save power. Advanced architectures like fully depleted SOI (FD-SOI) and multi-gate FETs (FinFETs, gate-all-around) provide better electrostatic control, which helps manage these trade-offs as devices continue to scale.