12.3 Lithography and patterning

Lithography and patterning are the steps in semiconductor fabrication where circuit designs actually get transferred onto the wafer. Without precise lithography, none of the other fabrication steps matter, because every transistor, interconnect, and contact hole starts as a pattern defined in photoresist. These processes determine the minimum feature size a fab can produce, which directly controls device density, speed, and power efficiency.

As feature sizes push below 10 nm, lithography runs into fundamental physical limits. Techniques like extreme ultraviolet (EUV) lithography and multiple patterning have been developed to work around these limits, and they're central to keeping pace with Moore's Law scaling.

Lithography process overview

Lithography transfers a pattern from a mask onto a thin layer of photoresist on the wafer surface. The process runs through a specific sequence of steps, each of which affects the final pattern quality. Getting any one step wrong can ruin critical dimensions across the entire wafer.

The main steps, in order:

1. Photoresist coating — spin-coat a uniform resist layer onto the wafer
2. Exposure — shine light (or other radiation) through a mask to selectively expose the resist
3. Post-exposure bake (PEB) — heat the wafer to activate chemical reactions in exposed regions
4. Development — dissolve away the soluble resist regions with a developer solution
5. Hard bake — further stabilize the remaining resist before etching or implantation

Photoresist coating

Photoresist is a light-sensitive polymer that gets spin-coated onto the wafer to form a thin, uniform layer. Spin speed and resist viscosity together control the film thickness, which typically ranges from tens of nanometers to a few micrometers depending on the exposure system and target resolution.

Before coating, an adhesion promoter such as hexamethyldisilazane (HMDS) is usually applied. HMDS converts the hydrophilic wafer surface to a hydrophobic one, which prevents the resist from peeling or lifting during development.

Exposure systems

Exposure systems use light or other radiation to transfer the mask pattern into the photoresist. The three main configurations differ in how the mask and wafer are positioned relative to each other:

• Contact printing — the mask sits directly on the photoresist. This gives high resolution because there's no gap for light to diffract through, but physical contact can damage the mask over repeated use.
• Proximity printing — a small gap (typically 10–50 µm) separates the mask from the resist. Mask damage is reduced, but diffraction across the gap degrades resolution.
• Projection printing — a lens system projects a demagnified image of the mask onto the wafer (commonly 4× reduction). This is the standard approach in modern fabs because it combines high resolution with minimal mask wear.

Post-exposure baking

After exposure, the wafer is baked at a controlled temperature (the post-exposure bake, or PEB). In chemically amplified resists (CARs), the PEB drives acid diffusion that amplifies the chemical change in exposed regions. This step also reduces standing wave effects, which are periodic intensity variations caused by reflections within the resist film.

Precise temperature control during PEB is critical. Even small temperature variations (on the order of 0.1°C) can shift critical dimensions, so modern bake plates use closed-loop thermal control.

Development

During development, a liquid developer selectively dissolves portions of the resist:

• For positive photoresists, the exposed regions dissolve away.
• For negative photoresists, the unexposed regions dissolve away.

The most common developer for positive resists is tetramethylammonium hydroxide (TMAH) at 0.26 N concentration. Development time and temperature must be tightly controlled to hit the target dimensions and avoid defects like pattern collapse (where tall, thin resist lines tip over) or incomplete removal.

Hard baking

After development, a hard bake further crosslinks the remaining photoresist, improving its thermal stability and chemical resistance. This matters because the resist needs to survive subsequent etching or ion implantation steps without deforming.

The hard bake temperature is chosen to be high enough to stabilize the resist but not so high that it causes the resist to flow and round off the pattern edges. Typical hard bake temperatures range from 100°C to 150°C depending on the resist chemistry.

Photolithography vs next-gen lithography

Optical lithography limitations

Conventional optical lithography is fundamentally limited by the diffraction of light. The minimum feature size (critical dimension) that can be resolved is described by the Rayleigh criterion:

$CD = k_1 \frac{\lambda}{NA}$

where $CD$ is the critical dimension, $k_1$ is a process-dependent factor (theoretically ≥ 0.25), $\lambda$ is the exposure wavelength, and $NA$ is the numerical aperture of the projection lens.

For 193 nm immersion lithography with $NA = 1.35$ and an aggressive $k_1 = 0.3$, the single-exposure resolution limit is roughly 43 nm. Reaching smaller features requires either shorter wavelengths, resolution enhancement techniques, or multiple patterning.

Extreme ultraviolet (EUV) lithography

EUV lithography uses a wavelength of 13.5 nm, which is about 14× shorter than 193 nm ArF lithography. This dramatic wavelength reduction enables single-exposure patterning of sub-10 nm features.

Because nearly all materials absorb strongly at 13.5 nm, EUV systems can't use conventional refractive lenses. Instead, they rely on multilayer reflective mirrors (alternating layers of Mo and Si) and reflective masks. EUV masks also cannot use traditional pellicles easily, which complicates defect protection.

Key challenges for EUV include generating sufficient source power for high throughput, controlling mask defects (since even tiny imperfections print at these scales), and developing resists that perform well at EUV wavelengths.

Electron beam lithography

Electron beam lithography (EBL) uses a focused beam of electrons to write patterns directly into the resist, with no mask required. Because electron wavelengths are far shorter than optical wavelengths, EBL can achieve sub-10 nm resolution.

The major drawback is throughput. EBL writes serially, pixel by pixel, making it far too slow for high-volume manufacturing. Its primary uses are:

• Writing the photomasks used in optical lithography
• Fabricating nanostructures for research
• Direct-write patterning for low-volume or prototype production

Nanoimprint lithography

Nanoimprint lithography (NIL) takes a mechanical approach: a pre-patterned mold is pressed into a resist layer to physically stamp the pattern. NIL can achieve sub-10 nm resolution and offers high throughput because the entire pattern transfers in parallel.

Challenges include fabricating defect-free molds, controlling defects introduced during the imprint process, and achieving the overlay accuracy needed for multilayer device fabrication.

Photoresists for lithography

Positive vs negative photoresists

Photoresists are classified by how their solubility changes upon exposure:

• Positive photoresists — exposed regions become more soluble in the developer. After development, the exposed areas are removed, so the pattern on the wafer matches the transparent regions of the mask.
• Negative photoresists — exposed regions become less soluble (typically through crosslinking). After development, the unexposed areas are removed, so the pattern is the inverse of the mask.

Positive resists generally offer better resolution and are more commonly used in advanced IC fabrication. Negative resists tend to have better adhesion and chemical resistance, making them useful for applications like thick-film patterning.

Photoresist composition

A typical photoresist has three main components:

• Polymer resin — provides the structural backbone and determines mechanical and thermal properties of the resist film.
• Photoactive compound (PAC) — responsible for the solubility change upon exposure. In conventional resists (like diazonaphthoquinone/novolac systems), the PAC undergoes a direct photochemical reaction. In chemically amplified resists, the PAC is a photoacid generator (PAG) that releases acid upon exposure, which then catalyzes many solubility-changing reactions during PEB.
• Solvent — controls viscosity for spin coating and evaporates during the soft bake step.

Photoresist properties and selection

When choosing a photoresist, you're balancing several key properties:

• Resolution — the smallest feature the resist can reliably reproduce.
• Sensitivity — the exposure dose (in mJ/cm²) needed to fully switch the resist's solubility. Higher sensitivity means faster exposure but can increase susceptibility to noise.
• Contrast — how sharply the resist transitions between soluble and insoluble states. High contrast produces steeper sidewall profiles.
• Etch resistance — how well the patterned resist holds up during subsequent plasma etching. Poor etch resistance leads to pattern erosion.

There's often a trade-off between these properties. For example, increasing sensitivity in EUV resists tends to degrade resolution and increase line edge roughness. Resist selection depends on the exposure system, target feature size, and downstream process requirements.

Resolution enhancement techniques

As optical lithography approaches its diffraction limits, several techniques squeeze better resolution out of existing systems.

Optical proximity correction (OPC)

OPC modifies the mask pattern to compensate for optical proximity effects, which cause features to print differently depending on their neighbors. Dense lines print differently from isolated lines, and corners tend to round off.

OPC algorithms adjust the mask in two main ways:

• Sub-resolution assist features (SRAFs) — small features added near isolated lines to make them behave optically like dense lines, improving process uniformity.
• Geometry adjustments — serifs added to corners, biasing of line widths, and other shape modifications to counteract predictable distortions.

Rule-based OPC applies predetermined corrections based on pattern geometry. Model-based OPC uses full lithography simulation to optimize corrections and is more accurate but computationally intensive.

Phase-shift masks (PSM)

Phase-shift masks exploit the phase of light, not just its amplitude, to improve resolution and contrast:

• Alternating PSM — adjacent transparent regions are given a 180° phase difference. Light from these regions destructively interferes at the boundary, creating a sharper dark line between features. This significantly improves contrast for dense patterns.
• Attenuated PSM — the nominally opaque regions transmit a small amount of light (typically 6%) with a 180° phase shift. This partially cancels the diffracted light at feature edges, improving resolution.

Off-axis illumination (OAI)

OAI modifies the shape of the illumination source to capture higher-order diffraction information:

• Annular illumination — a ring-shaped source that enhances resolution for dense patterns in all orientations.
• Dipole illumination — two source poles optimized for resolving dense lines along one direction.
• Quadrupole illumination — four source poles that improve resolution for dense patterns along two perpendicular directions (useful for Manhattan-geometry layouts).

OAI works by tilting the illumination angles so that more diffraction orders pass through the projection lens, which improves both resolution and depth of focus.

Multiple patterning

When single-exposure lithography can't resolve the target pitch, the pattern is split into two or more less-dense sub-patterns, each printed in a separate lithography-etch cycle.

• Double patterning (DP) splits one dense layer into two exposures, each at 2× the final pitch.
• Quadruple patterning (QP) uses four cycles to reach 4× pitch relaxation.

These techniques enabled 193 nm immersion lithography to pattern features well below its single-exposure limit (down to ~20 nm pitch with SAQP). The trade-offs are increased process complexity, tighter overlay requirements, and higher cost per layer.

Lithography process control

Critical dimension (CD) control

CD control means keeping feature sizes within a specified tolerance across the wafer and from wafer to wafer. Even small CD variations can shift transistor threshold voltages or change interconnect resistance.

Factors that affect CD include exposure dose, focus position, resist thickness uniformity, PEB temperature, and etch bias. These are monitored using in-line metrology:

• Scatterometry (OCD) — measures CD and profile shape by analyzing how light diffracts from periodic test structures. Fast and non-destructive.
• CD-SEM — uses a scanning electron microscope to directly image and measure feature widths. Higher resolution than scatterometry but slower.

Overlay accuracy

Overlay accuracy measures how well patterns from successive lithography layers align to each other. Modern devices require overlay errors below a few nanometers, since misalignment can cause shorts, opens, or degraded device performance.

Factors influencing overlay include wafer distortion (from thermal processing or film stress), lens distortion, stage positioning errors, and alignment mark quality. Overlay is measured using dedicated targets (like box-in-box or diffraction-based marks) with optical or e-beam metrology tools.

Defect inspection and metrology

Defect inspection identifies particles, pattern defects, and residues on the wafer that could kill devices or reduce yield. Both optical and electron beam inspection tools are used, with e-beam inspection offering higher sensitivity for smaller defects but at lower throughput.

Metrology provides quantitative process data, including CD measurements, film thickness, and sidewall angle. Feedback from inspection and metrology feeds back into process control loops, allowing engineers to adjust exposure dose, focus, overlay corrections, and other parameters to keep the process centered.

Advanced patterning techniques

Directed self-assembly (DSA)

DSA is a bottom-up approach that uses block copolymers to form ordered nanostructures through self-assembly. Block copolymers consist of two chemically distinct polymer chains bonded together. When annealed, they phase-separate into periodic domains (lamellae, cylinders, or spheres) with feature sizes determined by the polymer molecular weight.

To make DSA useful for IC patterning, the self-assembly is guided by lithographically defined templates (chemical or topographic). This combines the high resolution of self-assembly with the pattern placement control of conventional lithography.

Challenges include reducing defect density to acceptable levels, achieving precise pattern placement, and integrating DSA into existing process flows.

Spacer-defined multiple patterning

Spacer-defined patterning (also called self-aligned multiple patterning) doubles pattern density without requiring a second lithography step. The process works as follows:

1. Pattern a set of sacrificial mandrels using conventional lithography.
2. Deposit a conformal thin film (the spacer material) over the mandrels.
3. Etch the spacer film anisotropically to leave spacers only on the mandrel sidewalls.
4. Selectively remove the mandrels, leaving behind a spacer array at 2× the original density.

This sequence can be repeated: using the spacers as new mandrels for another round produces self-aligned quadruple patterning (SAQP), achieving 4× density multiplication. Advantages include inherent self-alignment and relaxed overlay requirements compared to litho-etch-litho-etch (LELE) double patterning.

Block copolymer lithography

Block copolymer lithography uses the self-assembly of block copolymers as a stand-alone patterning method. The process involves:

1. Depositing a block copolymer film on a substrate.
2. Annealing to induce phase separation into periodic nanodomains.
3. Selectively removing one polymer domain (e.g., by plasma etching or wet chemistry) to create a patterned template.

This technique can produce features below 10 nm with regular periodicity. It can also be combined with conventional lithography for pattern density multiplication. Current challenges are controlling defect density, achieving arbitrary (non-periodic) pattern layouts, and meeting the registration requirements of semiconductor manufacturing.

Lithography simulation and modeling

Aerial image simulation

Aerial image simulation calculates the light intensity distribution at the wafer plane based on the mask pattern, illumination source shape, and projection lens properties. Simulation tools use scalar or vector diffraction theory and account for partial coherence, lens aberrations, and polarization effects.

These simulations are used to evaluate and optimize mask designs, illumination conditions, and process parameters before committing to expensive mask fabrication and wafer processing.

Resist profile modeling

Resist profile modeling predicts the 3D shape of the developed resist pattern by simulating how the photoresist responds to the aerial image. The models incorporate resist absorption, photoacid generation and diffusion (for CARs), and development rate as a function of local chemical state.

Accurate resist modeling is important for predicting how changes in exposure dose, focus, and PEB conditions will affect the final resist profile, including sidewall angle, footing, and rounding.

Lithography process optimization

Process optimization finds the combination of parameters (exposure dose, focus, PEB temperature, development time, etc.) that produces the best pattern quality across the largest process window.

Common optimization approaches include:

• Design of experiments (DOE) — systematically varies multiple parameters to map out their effects and interactions.
• Response surface methodology (RSM) — fits a mathematical model to DOE data to find optimal operating points.
• Simulation-guided optimization — uses aerial image and resist models to predict outcomes, reducing the number of expensive wafer experiments needed.

The goals are to maximize the process window (the range of dose and focus over which CDs stay in spec), minimize CD variation, and maintain overlay accuracy.

Challenges in sub-10nm patterning

EUV source and optics

EUV lithography requires a high-power, stable source at 13.5 nm. Current sources use laser-produced plasma (LPP), where a high-power CO₂ laser strikes tin droplets to generate EUV radiation. Source power has been a persistent bottleneck: high-volume manufacturing requires >250 W at intermediate focus, and reaching this level with sufficient stability has taken years of development.

EUV optics use multilayer Mo/Si mirrors that achieve about 70% reflectivity per surface. With 10+ mirror surfaces in the optical path, total transmission is only a few percent, which is why source power requirements are so demanding. Mask defects are also a major concern, since any defect on the reflective mask blank can print as a pattern error.

Resist materials for EUV

EUV resists must simultaneously deliver high resolution, high sensitivity, and low line edge roughness (LER). These three requirements are in tension with each other, a trade-off known as the RLS triangle (Resolution-LER-Sensitivity).

Conventional chemically amplified resists struggle at EUV because the lower number of photons per feature (compared to 193 nm) increases photon shot noise, which directly worsens LER. Novel resist platforms under development include:

• Metal-oxide resists — inorganic resists with high EUV absorption and etch resistance.
• Molecular resists — small, uniform molecules that reduce the blur from acid diffusion in CARs.

Stochastic effects and line edge roughness

At sub-10 nm feature sizes, the number of photons and chemical events per feature becomes small enough that statistical fluctuations have a measurable impact. These stochastic effects include photon shot noise (random variation in the number of absorbed photons) and molecular-level fluctuations in resist chemistry.

The result is increased line edge roughness (LER) and line width roughness (LWR), where the edges of printed features are no longer smooth but exhibit random variations. For a 10 nm line, even 1–2 nm of LER represents a significant fraction of the feature width and can degrade transistor performance.

Strategies to mitigate stochastic effects include using higher-sensitivity resists (to increase the number of chemical events per photon), optimizing exposure and development conditions, and applying post-lithography smoothing techniques such as resist reflow or hydrogen plasma treatment.