Semiconductor Physics Unit 12 Review: Semiconductor Device Fabrication

Basic Semiconductor Materials

• Semiconductors are materials with electrical conductivity between conductors (metals) and insulators (ceramics)
• Most commonly used semiconductors are silicon (Si) and germanium (Ge)
  • Silicon is preferred due to its abundance, low cost, and stable oxide formation
• Other important semiconductors include gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC)
• Semiconductors have a band gap, which is the energy difference between the valence band and conduction band
  • Band gap determines the material's electrical and optical properties
• Intrinsic semiconductors are pure materials with equal numbers of electrons and holes
• Extrinsic semiconductors are doped with impurities to create n-type (excess electrons) or p-type (excess holes) materials

Crystal Structure and Growth

• Semiconductors have a regular, periodic arrangement of atoms called a crystal structure
• Most semiconductors have a diamond cubic crystal structure (Si, Ge) or zinc blende structure (GaAs, InP)
• Single-crystal semiconductors are grown using various techniques to ensure uniform properties throughout the material
• Czochralski (CZ) method is the most common technique for growing silicon single crystals
  • Involves pulling a seed crystal from a melt of pure silicon
• Float-zone (FZ) method produces high-purity silicon crystals by passing a molten zone through a polycrystalline rod
• Epitaxial growth techniques (MBE, MOCVD) are used to grow thin, single-crystal layers on a substrate
• Polycrystalline and amorphous semiconductors have less ordered structures and are used in some applications (solar cells, thin-film transistors)

Wafer Preparation

• Single-crystal semiconductor ingots are sliced into thin wafers using wire saws or diamond blades
• Wafers are typically 200-300 mm in diameter and 0.5-1 mm thick
• Wafer surfaces are polished using chemical-mechanical planarization (CMP) to achieve a smooth, flat surface
• Cleaning processes remove contaminants and native oxide from the wafer surface
  • RCA clean is a common two-step process using hydrogen peroxide, ammonia, and hydrochloric acid solutions
• Wafer orientation (crystal plane) is chosen based on the desired device properties and fabrication requirements
  • (100) orientation is most common for silicon devices
• Wafers are inspected for defects and sorted based on quality before proceeding to device fabrication

Doping Techniques

• Doping introduces impurities into the semiconductor to control its electrical properties
• n-type doping adds electron-donating impurities (phosphorus, arsenic) to create excess electrons
• p-type doping adds electron-accepting impurities (boron, gallium) to create excess holes
• Ion implantation accelerates dopant ions into the semiconductor surface
  • Precise control over dopant concentration and depth profile
  • Requires high-temperature annealing to activate dopants and repair crystal damage
• Diffusion doping involves heating the wafer in the presence of a dopant source (gas, solid, or spin-on source)
  • Dopants diffuse into the semiconductor based on concentration gradients and temperature
• In-situ doping incorporates dopants during epitaxial growth, allowing for precise control of doping profiles
• Doping concentration and profile are critical for determining device characteristics (threshold voltage, conductivity)

Lithography Process

• Lithography transfers patterns from a mask to the wafer surface using light, electrons, or ions
• Photolithography is the most common technique, using UV light to expose a light-sensitive polymer (photoresist)
  • Positive photoresist becomes soluble in developer when exposed; negative photoresist becomes insoluble
• Exposure systems include contact, proximity, and projection (stepper or scanner) tools
  • Resolution is limited by the wavelength of light and the numerical aperture of the lens system
• Electron beam lithography (EBL) uses a focused electron beam to directly write patterns on the wafer
  • Higher resolution than photolithography but slower and more expensive
• Nanoimprint lithography (NIL) physically deforms a resist using a mold, enabling high-resolution patterning
• Resolution enhancement techniques (OPC, PSM) improve pattern fidelity and enable smaller feature sizes
• Development removes exposed (positive) or unexposed (negative) photoresist, creating a patterned mask for subsequent processing

Etching Methods

• Etching selectively removes material from the wafer surface based on the lithographic pattern
• Wet etching uses liquid chemicals (acids, bases) to dissolve the exposed material
  • Isotropic etching occurs equally in all directions, resulting in undercut profiles
  • Anisotropic wet etching (e.g., KOH on silicon) follows specific crystal planes, creating faceted profiles
• Dry etching uses plasma-generated reactive species to remove material
  • Reactive ion etching (RIE) combines chemical and physical etching for anisotropic profiles
  • Deep reactive ion etching (DRIE) alternates etching and passivation steps to create high-aspect-ratio features
• Selectivity refers to the etch rate difference between the target material and the mask or underlying layers
• Etch rate, uniformity, and profile control are critical for achieving the desired device dimensions and performance

Thin Film Deposition

• Thin film deposition creates layers of materials on the wafer surface for various purposes (insulation, conductivity, passivation)
• Physical vapor deposition (PVD) techniques include evaporation and sputtering
  • Evaporation heats the source material to produce a vapor that condenses on the wafer
  • Sputtering uses ion bombardment to physically eject atoms from a target onto the wafer
• Chemical vapor deposition (CVD) uses gas-phase precursors that react on the wafer surface to form a film
  • Low-pressure CVD (LPCVD) operates at reduced pressures for improved uniformity and step coverage
  • Plasma-enhanced CVD (PECVD) uses plasma to lower deposition temperatures and enhance reaction rates
• Atomic layer deposition (ALD) grows films one atomic layer at a time using self-limiting surface reactions
  • Enables precise thickness control and conformal coverage of high-aspect-ratio features
• Spin coating deposits liquid-phase materials (photoresist, spin-on glass) by spinning the wafer at high speeds
• Film thickness, uniformity, and adhesion are important factors in thin film deposition processes

Oxidation and Diffusion

• Thermal oxidation grows a silicon dioxide (SiO2) layer on the silicon surface by exposing it to oxygen or water vapor at high temperatures
  • Dry oxidation (O2) produces a denser, higher-quality oxide; wet oxidation (H2O) has a faster growth rate
• Oxide thickness is controlled by temperature, time, and ambient conditions
  • Deal-Grove model describes the oxidation kinetics based on diffusion and reaction rates
• Oxides serve as insulators, masks for doping and etching, and gate dielectrics in transistors
• Thermal diffusion is used to drive dopants deeper into the semiconductor or to redistribute dopant profiles
  • Fick's laws describe the diffusion process based on concentration gradients and temperature
• Diffusion is performed in a furnace with a controlled ambient (N2, O2, or dopant sources)
• Diffusion profile depends on the initial dopant distribution, temperature, time, and semiconductor properties
• Oxidation and diffusion are often combined to create self-aligned device structures (e.g., LOCOS isolation)

Metallization and Interconnects

• Metallization creates conductive paths (interconnects) to connect device components and provide external contacts
• Aluminum (Al) is the most common metal for interconnects due to its low resistivity and good adhesion
  • Copper (Cu) is increasingly used for advanced devices due to its lower resistivity and improved electromigration resistance
• Metal films are deposited using PVD (sputtering) or CVD techniques
• Patterning of metal layers is done using lithography and etching processes
  • Damascene process involves etching trenches or vias in a dielectric layer and filling them with metal
• Multiple metal layers are separated by insulating layers (inter-layer dielectrics) and connected by vertical vias
• Planarization techniques (CMP) are used to flatten the wafer surface after each metal layer
• Challenges in metallization include minimizing resistance, ensuring reliability, and reducing interconnect delays
• Advanced interconnect materials (low-k dielectrics, barrier layers) are used to improve performance and reliability

Packaging and Testing

• Packaging provides mechanical support, environmental protection, and electrical connections for the finished device
• Dicing separates the individual devices (dies) from the wafer using a diamond saw or laser
• Die bonding attaches the die to a package substrate or leadframe using adhesives or solders
• Wire bonding connects the die bond pads to the package leads using thin metal wires (Au, Al, Cu)
  • Flip-chip bonding directly connects the die to the substrate using solder bumps, eliminating the need for wire bonds
• Encapsulation protects the die and wire bonds using a plastic molding compound or ceramic lid
• Testing is performed at various stages of fabrication (in-line, wafer-level, package-level) to ensure device quality and reliability
  • Electrical tests measure device parameters (voltage, current, capacitance) and verify functionality
  • Burn-in tests operate devices at elevated temperatures and voltages to screen for early failures
• Packaging and testing account for a significant portion of the total manufacturing cost and are critical for yield and reliability

Advanced Fabrication Techniques

• Strained silicon enhances carrier mobility by introducing lattice strain using epitaxial growth of SiGe layers
• High-k/metal gate stacks replace SiO2/polysilicon gates to reduce leakage current and enable further scaling
  • High-k dielectrics (HfO2, ZrO2) have higher permittivity, allowing for thicker layers with the same capacitance
  • Metal gates (TiN, TaN) eliminate polysilicon depletion effects and improve work function control
• FinFET (fin field-effect transistor) is a 3D transistor structure that provides better electrostatic control and reduced short-channel effects
  • Consists of a thin vertical "fin" of silicon surrounded by the gate on three sides
• Gate-all-around (GAA) FETs use nanowire or nanosheet channels completely surrounded by the gate for ultimate scalability
• 3D integration (3D-IC) stacks multiple device layers vertically using through-silicon vias (TSVs) to improve performance and density
• Wafer-level packaging (WLP) integrates packaging processes at the wafer level, reducing size and cost
• Advanced lithography techniques (EUV, directed self-assembly) enable patterning of ever-smaller features
• Novel materials (III-V semiconductors, 2D materials) are being explored for future generations of devices