8.5 Scaling and short-channel effects

Scaling semiconductor devices is crucial for improving performance and efficiency in electronics. As dimensions shrink, short-channel effects emerge, impacting device behavior. Understanding these effects is key to overcoming challenges in modern semiconductor technology.

Velocity saturation, threshold voltage roll-off, and drain-induced barrier lowering are some short-channel effects that arise in scaled devices. Engineers use techniques like substrate engineering, lightly doped drains, and multi-gate architectures to mitigate these issues and push the limits of conventional MOSFETs.

Scaling of semiconductor devices

• Scaling involves reducing the dimensions of semiconductor devices to improve performance, increase density, and reduce power consumption
• As devices are scaled down, various short-channel effects emerge that can degrade device performance and reliability
• Scaling has been a key driver of the semiconductor industry, enabling the development of faster, more powerful, and more efficient electronic devices

Short-channel effects in MOSFETs

Velocity saturation vs channel length

• As channel length decreases, the electric field in the channel increases, causing carrier velocity to saturate at a maximum value
• Velocity saturation limits the maximum current that can flow through the device, reducing the benefits of scaling
• The onset of velocity saturation occurs at shorter channel lengths for higher mobility materials (III-V semiconductors) compared to silicon

Threshold voltage roll-off

• Threshold voltage roll-off is a reduction in the threshold voltage of a MOSFET as the channel length decreases
• Caused by the increased influence of source and drain depletion regions on the channel potential
• Results in higher off-state leakage current and reduced control over the device switching characteristics
• Can be mitigated by adjusting the doping profile in the channel region (retrograde doping)

Drain-induced barrier lowering (DIBL)

• DIBL occurs when the drain voltage influences the potential barrier at the source-channel junction, lowering the threshold voltage
• More pronounced in short-channel devices due to the closer proximity of the drain to the source
• Leads to increased off-state leakage current and reduced device performance
• Can be mitigated by using shallow source/drain junctions and halo implants

Hot carrier effects in short channels

• High electric fields in short-channel devices can accelerate carriers (electrons or holes) to very high energies, creating "hot" carriers
• Hot carriers can inject into the gate oxide, causing damage and degrading device reliability
• Can also generate electron-hole pairs through impact ionization, leading to substrate current and parasitic bipolar effects
• Mitigated by using lightly doped drain (LDD) structures and optimizing device geometry

Impact ionization and avalanche breakdown

• Impact ionization occurs when high-energy carriers collide with the lattice, generating electron-hole pairs
• In short-channel devices, the high electric fields can trigger avalanche multiplication of carriers, leading to a rapid increase in current
• Avalanche breakdown can cause permanent damage to the device and limit the maximum operating voltage
• Can be suppressed by using LDD structures and carefully designing the doping profiles

Techniques for mitigating short-channel effects

Substrate engineering for improved performance

• Substrate engineering involves optimizing the doping profile in the substrate to control the electric field distribution
• Retrograde doping (higher doping concentration away from the surface) helps to reduce threshold voltage roll-off and DIBL
• Super-steep retrograde (SSR) doping profiles can further improve short-channel characteristics
• Germanium-on-insulator (GeOI) substrates offer higher mobility and better short-channel performance compared to silicon

Lightly doped drain (LDD) structures

• LDD structures feature a lightly doped region between the heavily doped source/drain and the channel
• The lightly doped region reduces the peak electric field near the drain, mitigating hot carrier effects and impact ionization
• LDD structures also help to reduce parasitic capacitances and improve device speed
• Fabricated using a double implantation process with spacers to control the LDD region dimensions

Halo implantation and pocket implants

• Halo implantation involves introducing a localized, heavily doped region near the source and drain junctions
• The halo regions help to control the channel potential and reduce DIBL and threshold voltage roll-off
• Pocket implants are similar to halo implants but are typically formed using a tilted ion implantation process
• Both techniques help to improve short-channel characteristics and maintain device performance at smaller dimensions

Silicon-on-insulator (SOI) devices

• SOI devices are fabricated on a layered substrate consisting of a thin silicon layer on top of an insulating oxide layer
• The buried oxide layer reduces parasitic capacitances and improves device isolation
• Fully-depleted SOI (FD-SOI) devices offer better electrostatic control and reduced short-channel effects compared to bulk silicon devices
• SOI technology enables the fabrication of ultra-thin body and buried oxide (UTBB) devices for improved scalability

Multi-gate transistor architectures

• Multi-gate transistors, such as FinFETs and tri-gate devices, feature a three-dimensional gate structure that wraps around the channel
• The increased gate control helps to suppress short-channel effects and improve device performance
• Multi-gate architectures enable the scaling of transistors to sub-20nm dimensions
• Challenges include increased process complexity and higher parasitic capacitances compared to planar devices

Scaling limits of conventional MOSFETs

Quantum mechanical tunneling and leakage

• As device dimensions shrink, quantum mechanical effects become more pronounced
• Tunneling of carriers through the thin gate oxide can lead to increased leakage current and power dissipation
• Band-to-band tunneling (BTBT) in the drain region can also contribute to leakage in short-channel devices
• Tunneling effects can be mitigated by using high-k dielectrics and optimizing device geometry

Gate oxide reliability vs scaling

• The gate oxide thickness must scale down with the device dimensions to maintain control over the channel
• Thinner gate oxides are more susceptible to breakdown and reliability issues, such as time-dependent dielectric breakdown (TDDB)
• The increased electric fields in scaled devices can also accelerate oxide degradation mechanisms
• High-k dielectrics and metal gates can help to mitigate gate oxide reliability issues while enabling further scaling

Process variations and statistical variability

• As devices scale down, the impact of process variations on device characteristics becomes more significant
• Statistical variability, such as random dopant fluctuations (RDF) and line edge roughness (LER), can cause variations in threshold voltage and device performance
• Process variations can lead to reduced yield and increased design complexity for advanced technology nodes
• Techniques such as statistical design optimization and post-silicon tuning can help to mitigate the impact of process variations

Advanced transistor structures for continued scaling

High-k dielectrics and metal gates

• High-k dielectrics, such as hafnium oxide (HfO2), have a higher dielectric constant than silicon dioxide (SiO2)
• The use of high-k dielectrics allows for a thicker physical oxide thickness while maintaining the same equivalent oxide thickness (EOT) as a thinner SiO2 layer
• Metal gates, such as titanium nitride (TiN) or tantalum nitride (TaN), replace polysilicon gates to eliminate poly depletion effects and improve device performance
• The combination of high-k dielectrics and metal gates enables the scaling of gate stacks to sub-1nm EOT

Strained silicon for enhanced mobility

• Strained silicon involves introducing a tensile or compressive strain in the silicon lattice to modify the band structure
• Tensile strain increases electron mobility, while compressive strain enhances hole mobility
• Strained silicon can be achieved through epitaxial growth of silicon on relaxed SiGe buffer layers (global strain) or by using stress liners and embedded SiGe source/drain regions (local strain)
• Strained silicon helps to improve device performance and can be combined with other scaling techniques

Vertical and 3D transistor architectures

• Vertical transistors, such as vertical nanowire FETs and vertical-channel FETs, feature a channel that is perpendicular to the substrate surface
• The vertical geometry allows for better electrostatic control and higher device density compared to planar architectures
• 3D integration techniques, such as through-silicon vias (TSVs) and monolithic 3D (M3D) integration, enable the stacking of multiple device layers
• 3D transistor architectures help to overcome the scaling limitations of conventional planar devices and enable the continued scaling of transistor density

Nanowire and nanosheet FETs

• Nanowire FETs feature a cylindrical channel surrounded by a gate, offering excellent electrostatic control and reduced short-channel effects
• Nanosheet FETs have a channel composed of multiple horizontal nanowire-like sheets, providing a larger effective channel width and improved performance
• Both nanowire and nanosheet FETs can be fabricated using bottom-up or top-down approaches
• These novel device architectures are promising candidates for scaling beyond the limits of FinFET technology

Carbon nanotube and graphene-based devices

• Carbon nanotubes (CNTs) and graphene are one-dimensional and two-dimensional allotropes of carbon, respectively, with unique electronic properties
• CNT-based FETs can exhibit ballistic transport and high mobility, making them attractive for high-performance applications
• Graphene-based devices, such as graphene nanoribbons (GNRs) and bilayer graphene FETs, offer the potential for ultra-fast switching and low power consumption
• Challenges include the precise control of CNT chirality and placement, as well as the opening of a bandgap in graphene for digital logic applications
• Despite the challenges, carbon-based devices are an active area of research for post-silicon electronics