3.4 Examples of common ISAs (e.g., x86, ARM, MIPS)

Key features of ISAs

Instruction Set Architecture definition and role

An Instruction Set Architecture (ISA) defines the interface between hardware and software. It specifies which instructions a processor supports, what registers are available, how memory is addressed, and what data types the hardware can work with.

Think of the ISA as a contract: software written to a particular ISA will run on any processor that implements it. This is what makes compatibility and portability possible. You can upgrade your CPU and your old programs still work, as long as the new chip supports the same ISA.

Register types and functions

The number and types of registers vary across ISAs, but they generally fall into two categories:

• General-purpose registers handle arithmetic, logical, and memory operations. These are the registers you'll use most when writing assembly.
• Special-purpose registers serve specific roles:
  • Program counter (PC) stores the address of the next instruction to execute
  • Stack pointer (SP) points to the top of the call stack
  • Status/flag register holds condition flags from the last operation (like whether the result was zero or caused an overflow)

The number of general-purpose registers matters a lot for performance. More registers mean fewer trips to memory, which speeds things up.

Memory addressing modes

Addressing modes determine how an instruction specifies where its data lives. Here are the most common ones:

• Immediate: the data value is embedded directly in the instruction itself (e.g., "add 5 to register R1")
• Direct: the instruction contains the memory address where the data is stored
• Register indirect: a register holds the memory address of the data
• Indexed: a base address plus an offset gives the final address, useful for accessing array elements
• PC-relative: the address is calculated relative to the program counter, commonly used for branch instructions
• Stack-based: data is accessed relative to the stack pointer

Different ISAs support different subsets of these modes. CISC architectures tend to support more modes, while RISC architectures keep things simpler.

RISC vs CISC architectures

This is one of the most fundamental distinctions in ISA design.

RISC (Reduced Instruction Set Computing) uses a smaller set of simple, fixed-length instructions. The idea is that simpler instructions can be executed faster and are easier to pipeline. Examples: ARM, MIPS, RISC-V.

CISC (Complex Instruction Set Computing) uses a larger set of complex, variable-length instructions. A single CISC instruction might do what takes several RISC instructions. This can produce more compact code and was historically important when memory was expensive. Examples: x86, VAX, IBM System/360.

Instruction format and endianness

Instruction length affects several things at once. Fixed-length instructions (typical of RISC) simplify decoding and make pipelining straightforward, since the processor always knows where the next instruction starts. Variable-length instructions (typical of CISC) can pack more information into fewer bytes, producing denser code but making decoding harder.

Endianness refers to byte ordering in memory:

• Little-endian: the least significant byte is stored at the lowest address (x86 uses this)
• Big-endian: the most significant byte is stored at the lowest address

Some architectures (like ARM) are bi-endian, meaning they can operate in either mode. Endianness matters when systems exchange binary data or when you're debugging at the byte level.

x86 vs ARM vs MIPS Architectures

x86 architecture

x86 is the dominant ISA in desktops, laptops, and servers. It's a CISC architecture with variable-length instructions ranging from 1 to 15 bytes and over 1,000 instructions in its modern form.

• Supports complex memory addressing modes, meaning arithmetic instructions can operate directly on memory (not just registers)
• Backward compatibility is a defining trait: code written for the original 8086 in 1978 can still run on a modern Intel or AMD chip
• Has relatively few general-purpose registers: 8 in 32-bit mode, 16 in 64-bit mode (x86-64)
• Found in processors like Intel Core and AMD Ryzen

The small register count is a historical limitation. Compilers have to spill values to memory more often than on register-rich RISC architectures.

ARM architecture

ARM is a RISC architecture that dominates mobile devices, tablets, and embedded systems. Energy efficiency is its core design goal.

• Uses fixed-length 32-bit instructions with a relatively small instruction set (100-200 instructions)
• Follows a load-store architecture: all arithmetic and logic operations work only on registers. You must explicitly load data from memory into a register before operating on it, then store results back.
• Provides 16 general-purpose registers in 32-bit mode (AArch32) and 31 in 64-bit mode (AArch64)
• Powers chips from Qualcomm (Snapdragon), Apple (M-series, A-series), and Samsung (Exynos)

ARM's licensing model is unique: ARM Holdings designs the ISA and licenses it to other companies, who then build their own chips around it. This has driven massive adoption and competition.

MIPS architecture

MIPS is another RISC architecture, best known for its clean, simple design. It's a favorite in computer architecture courses for exactly that reason.

• Uses fixed-length 32-bit instructions, similar in count to ARM
• Has 32 general-purpose registers, with register $\$0$ hardwired to always contain zero (useful for common operations like clearing a register or comparing against zero)
• Historically used in gaming consoles (PlayStation 1/2, Nintendo 64) and networking equipment
• Its straightforward pipeline design makes it an excellent teaching tool for understanding how processors execute instructions

MIPS has declined in commercial use compared to ARM, but its influence on ISA design and computer science education remains significant.

Comparison of instruction sets and features

x86 supports complex single instructions (string manipulation, transcendental math functions) that ARM and MIPS handle through software libraries or sequences of simpler instructions. On the other hand, ARM and MIPS benefit from more registers and simpler decoding logic.

Evolution of ISAs

Historical development

• x86 originated with Intel's 8086 processor in 1978. It evolved through the 80286, 80386 (which introduced 32-bit), Pentium series, and into today's Core and Ryzen families, always maintaining backward compatibility.
• ARM (originally Acorn RISC Machine) was developed by Acorn Computers in the 1980s and later spun off into ARM Holdings, which licenses the architecture to chip manufacturers worldwide.
• MIPS (Microprocessor without Interlocked Pipeline Stages) was developed by MIPS Computer Systems in the 1980s, growing out of research at Stanford University.

Impact of mobile computing and energy efficiency

The smartphone revolution dramatically shifted the ISA landscape. ARM's low-power design made it the natural fit for battery-powered devices, and it now ships in billions of chips per year.

ARM's licensing model allowed companies like Qualcomm, Apple, and Samsung to design custom chips tailored to their products. This fostered rapid innovation. Apple's transition from Intel x86 to its own ARM-based M-series chips in Macs showed that ARM can compete with x86 even in laptop and desktop performance.

x86 has responded with more energy-efficient designs like Intel Atom and AMD's embedded Ryzen processors, but ARM remains dominant in mobile and is gaining ground in servers (Amazon's Graviton, for example).

64-bit extensions and modern computing demands

All three ISAs have developed 64-bit extensions: x86-64 (also called AMD64), ARMv8 (AArch64), and MIPS64. The move to 64-bit brought several benefits:

• Access to much larger memory spaces (beyond the 4 GB limit of 32-bit addressing)
• More registers available to programs
• Better performance for workloads like scientific computing, databases, and virtualization

This transition was driven by growing data sizes. Applications in machine learning, data analytics, and high-performance computing routinely need to address more than 4 GB of memory.

Convergence of ISA features

Over time, the strict RISC vs. CISC divide has blurred considerably.

Modern x86 processors internally translate complex CISC instructions into simpler micro-operations (micro-ops) that execute on a RISC-like pipeline. So from the outside, x86 looks like CISC, but internally it behaves more like RISC.

Meanwhile, ARM and MIPS have added SIMD (Single Instruction, Multiple Data) extensions for parallel processing. ARM NEON and MIPS MSA allow a single instruction to operate on multiple data elements simultaneously, boosting performance in multimedia, signal processing, and machine learning tasks.