7.4 Transistors

Basic transistor structure

A transistor is a semiconductor device that controls current flow using a small input signal, acting as either an amplifier or a switch. Every transistor relies on the same core physics: manipulating charge carriers at junctions between differently doped semiconductor regions.

Semiconductor materials

Silicon dominates transistor fabrication because of its abundant supply, stable native oxide ($SiO_2$), and well-understood processing. Other materials fill specialized roles:

• Germanium has higher carrier mobility than silicon but a smaller band gap ($\sim 0.67 \text{ eV}$ vs. $\sim 1.12 \text{ eV}$), making it useful for high-speed p-channel devices.
• Compound semiconductors like $GaAs$ and $InP$ offer direct band gaps and very high electron mobility, which is why they appear in RF and optoelectronic applications.

The band gap energy of a semiconductor sets the boundary between insulating and conducting behavior. A larger band gap means fewer thermally excited carriers at room temperature, which affects leakage current and maximum operating temperature. Crystal structure also matters: carrier mobility depends on how easily electrons and holes move through the lattice.

P-n junctions

The p-n junction is the fundamental building block of every transistor. When p-type and n-type semiconductors are brought together:

1. Electrons from the n-side and holes from the p-side diffuse across the boundary and recombine near the interface.
2. This leaves behind fixed ionized dopant atoms, creating a depletion region that's depleted of free carriers.
3. The exposed charges produce a built-in electric field that opposes further diffusion, establishing a built-in potential (typically $\sim 0.7 \text{ V}$ for silicon).

Biasing changes the junction behavior:

• Forward bias (positive voltage applied to p-side) shrinks the depletion region and lowers the potential barrier, allowing current to flow.
• Reverse bias (positive voltage applied to n-side) widens the depletion region and raises the barrier, blocking current flow except for a tiny leakage current.

Doping in transistors

Doping means intentionally introducing impurity atoms into a semiconductor to control its electrical properties.

• N-type doping uses donor atoms with five valence electrons (phosphorus, arsenic). Each donor contributes one extra electron to the conduction band.
• P-type doping uses acceptor atoms with three valence electrons (boron, gallium). Each acceptor creates a hole in the valence band.

Doping concentration directly controls carrier density and conductivity. In a transistor, different regions are doped to different levels. For example, in a BJT the emitter is heavily doped to inject carriers efficiently, while the base is lightly doped and kept thin. This precise spatial control of doping profiles is what gives each transistor region its distinct electrical role.

Types of transistors

Transistors fall into two broad families based on how they control current: bipolar junction transistors (BJTs) use current injection, while field-effect transistors (FETs) use an electric field. Choosing between them depends on the application's requirements for gain, impedance, power, and speed.

Bipolar junction transistors

A BJT has three doped regions forming two back-to-back p-n junctions:

• Emitter: heavily doped, injects carriers into the base.
• Base: thin and lightly doped, controls the flow of carriers.
• Collector: moderately doped, collects carriers that make it through the base.

Two configurations exist: NPN (n-emitter, p-base, n-collector) and PNP (p-emitter, n-base, p-collector). In an NPN transistor, a small base current allows a much larger current to flow from collector to emitter. The ratio of collector current to base current is the current gain $\beta$, which characterizes the transistor's amplification capability.

BJTs are current-controlled devices. They excel in analog amplification and power applications where high transconductance and drive capability matter.

Field-effect transistors

FETs control current through a conducting channel between the source and drain terminals by applying a voltage to the gate. No gate current is needed in the ideal case, which gives FETs very high input impedance.

• JFET (Junction FET): The gate forms a reverse-biased p-n junction with the channel. Increasing the reverse bias widens the depletion region, pinching off the channel and reducing current.
• FETs come in depletion-mode (channel exists at zero gate voltage, gate voltage turns it off) and enhancement-mode (no channel at zero gate voltage, gate voltage creates one).

Because FETs are voltage-controlled and draw negligible gate current, they're well suited for high-impedance input stages and low-power circuits.

MOSFET vs JFET

The MOSFET (Metal-Oxide-Semiconductor FET) differs from the JFET in one critical way: its gate is insulated from the channel by a thin oxide layer ($SiO_2$ or high-k dielectric). This insulation gives the MOSFET an even higher input impedance than a JFET and virtually eliminates DC gate current.

Transistor operation principles

Carrier transport mechanisms

Two mechanisms drive current inside a transistor:

• Drift current: Carriers accelerate under an applied electric field. This dominates in the channel of a FET and in the collector region of a BJT.
• Diffusion current: Carriers move from regions of high concentration to low concentration. This is the primary mechanism in the base region of a BJT, where injected minority carriers diffuse across to the collector.

Recombination (an electron fills a hole, both carriers are lost) and generation (thermal energy creates an electron-hole pair) affect carrier lifetimes. In a BJT, you want minimal recombination in the base so that most injected carriers reach the collector, which is why the base is kept thin.

• BJTs rely on minority carrier injection (electrons injected into the p-type base of an NPN).
• FETs rely on majority carrier transport (electrons flowing through an n-channel, or holes through a p-channel).

Current amplification

In a BJT (common-emitter configuration), a small base current $I_B$ controls a much larger collector current $I_C$. The current gain is:

$\beta = \frac{I_C}{I_B}$

Typical $\beta$ values range from 50 to 300 depending on the device.

In a FET, amplification is characterized by transconductance:

$g_m = \frac{\Delta I_D}{\Delta V_{GS}}$

This tells you how much the drain current $I_D$ changes for a small change in gate-source voltage $V_{GS}$. Higher $g_m$ means stronger amplification. Both gain and transconductance depend on device geometry, doping, and the chosen bias point. There's always a trade-off between gain, bandwidth, and power consumption.

Voltage control

• In a MOSFET, applying a gate voltage $V_{GS}$ above the threshold voltage $V_{th}$ creates an inversion layer (the channel) that allows current to flow between source and drain. Below $V_{th}$, the transistor is in the subthreshold region, where current drops exponentially but doesn't reach zero. This subthreshold regime is exploited in ultra-low-power circuits.
• In a BJT, the base-emitter voltage $V_{BE}$ controls the collector current exponentially: $I_C \propto e^{V_{BE}/V_T}$, where $V_T = kT/q \approx 26 \text{ mV}$ at room temperature.

In both cases, the transistor acts as a voltage-controlled current source in its active (or saturation, for MOSFETs) region.

Transistor characteristics

I-V curves

I-V curves are plots of current vs. voltage that map out a transistor's behavior across operating regions. They're essential for choosing bias points and understanding device limits.

• BJT output characteristics: Plot $I_C$ vs. $V_{CE}$ for several fixed values of $I_B$. You'll see a steep rise in the active region, then relatively flat curves where $I_C$ is controlled mainly by $I_B$.
• FET transfer characteristics: Plot $I_D$ vs. $V_{GS}$. For an enhancement-mode MOSFET, current is negligible below $V_{th}$, then rises (quadratically in saturation).
• Saturation region (MOSFET): The channel is pinched off near the drain, and $I_D$ becomes relatively independent of $V_{DS}$. This is the region used for amplification.
• Linear (triode) region (MOSFET): The channel is fully formed, and the transistor behaves like a voltage-controlled resistor. Useful for analog switches.

Gain and transconductance

• BJT current gain $\beta$ typically falls between 50 and 300. It varies with temperature, collector current, and frequency.
• FET transconductance $g_m$ depends on bias current and device dimensions. For a MOSFET in saturation: $g_m = \sqrt{2 \mu_n C_{ox} \frac{W}{L} I_D}$, where $W/L$ is the width-to-length ratio of the channel.
• Early voltage $V_A$ in BJTs quantifies how much $I_C$ increases with $V_{CE}$ in the active region. Higher $V_A$ means flatter output curves and higher output resistance.
• Channel length modulation is the FET equivalent: as $V_{DS}$ increases, the effective channel shortens slightly, causing $I_D$ to increase. The parameter $\lambda$ captures this effect.

Frequency response

Transistors can't amplify signals at arbitrarily high frequencies. Internal capacitances (junction capacitances in BJTs, gate-oxide and overlap capacitances in MOSFETs) limit speed.

• Cut-off frequency $f_T$: the frequency at which short-circuit current gain drops to 1. This is the most common figure of merit for transistor speed.
• Maximum oscillation frequency $f_{max}$: the frequency at which power gain drops to 1.
• The Miller effect multiplies the effective input capacitance in common-emitter/common-source configurations because the gate-drain (or base-collector) capacitance gets amplified by the voltage gain. This is often the dominant bandwidth limitation.
• Carrier transit time through the base (BJT) or channel (FET) and parasitic capacitances from interconnects also limit high-frequency performance.

Transistor applications

Amplifiers and switches

Transistors serve two fundamental roles: amplifying analog signals and switching digital signals.

Amplifier configurations (for BJTs):

• Common-emitter: High voltage and current gain, most widely used. Inverts the signal.
• Common-base: Low input impedance, no current gain, but excellent high-frequency performance.
• Common-collector (emitter follower): Voltage gain near 1, but high current gain and low output impedance. Used as a buffer.

FETs have analogous configurations (common-source, common-gate, common-drain).

Switching: A transistor driven between cut-off (off) and saturation (on) acts as an electronic switch. The transition between these states happens in nanoseconds or less, which is the basis of all digital electronics. Power transistors switch high-current loads like motors and speakers.

Logic gates

Digital logic is built from transistors acting as switches.

• CMOS (Complementary MOS) pairs an NMOS transistor with a PMOS transistor. In any stable logic state, one transistor is off, so almost no static current flows. This is why CMOS dominates modern digital design: it consumes power mainly during switching.
• A CMOS inverter is the simplest gate: when the input is high, the NMOS turns on and pulls the output low; when the input is low, the PMOS turns on and pulls the output high.
• NAND and NOR gates combine multiple transistors and serve as universal gates from which any logic function can be built.
• Older TTL (Transistor-Transistor Logic) used BJTs and was standard before CMOS took over.

Integrated circuits

Transistors are fabricated by the billions on single silicon chips, enabling complex systems in a tiny area.

• Microprocessors contain billions of MOSFETs implementing logic, cache memory, and control circuits.
• SRAM uses six transistors per bit for fast, volatile storage. DRAM uses one transistor and one capacitor per bit for denser but slower storage.
• Analog ICs combine transistors with resistors and capacitors for functions like amplification, filtering, and voltage regulation.
• Mixed-signal ICs integrate both analog and digital blocks on one chip (e.g., analog-to-digital converters).

Quantum effects in transistors

As transistor dimensions shrink below roughly 10 nm, classical models break down and quantum mechanics becomes essential for understanding device behavior.

Tunneling phenomena

Quantum tunneling is the process by which an electron passes through a potential energy barrier that it classically couldn't surmount. The tunneling probability depends exponentially on barrier thickness and height.

• Gate oxide leakage: When the gate oxide in a MOSFET is only a few atomic layers thick ($< 2 \text{ nm}$), electrons tunnel directly through it, causing unwanted leakage current. This was a major driver behind the switch from $SiO_2$ to high-k dielectrics.
• Tunnel FETs (TFETs): These exploit band-to-band tunneling at a reverse-biased p-n junction to achieve subthreshold swings below the 60 mV/decade thermal limit of conventional MOSFETs. This could enable much lower operating voltages.
• Resonant tunneling diodes use quantum wells to create discrete energy levels. Electrons tunnel efficiently only when their energy matches a well state, producing a region of negative differential resistance in the I-V curve.

Tunneling sets a fundamental limit on how thin barriers can be made, which constrains conventional transistor scaling.

Quantum confinement

When a semiconductor dimension shrinks to the scale of the electron's de Broglie wavelength (a few nanometers in silicon), the energy spectrum becomes discrete rather than continuous. This is quantum confinement.

• Quantum wells confine carriers in one dimension, creating a 2D electron gas (2DEG). This is the basis of HEMTs.
• Quantum wires confine in two dimensions (1D transport).
• Quantum dots confine in all three dimensions, producing atom-like discrete energy levels.

Confinement changes the density of states, which in turn affects carrier concentration, mobility, and optical properties. These effects are not just theoretical curiosities; they're actively exploited in real devices.

Single-electron transistors

A single-electron transistor (SET) controls the flow of individual electrons through a nanoscale island (quantum dot) coupled to source and drain by tunnel junctions.

The key phenomenon is Coulomb blockade: adding one electron to the island costs a charging energy $E_C = e^2 / 2C$, where $C$ is the island's total capacitance. If $E_C \gg k_B T$, thermal energy can't overcome this barrier, and electron transport is blocked until the gate voltage is tuned to allow the next electron on.

SETs currently require cryogenic temperatures ($T < 1 \text{ K}$) because the charging energy must exceed thermal fluctuations. Potential applications include quantum computing qubits and ultra-sensitive electrometers, but room-temperature operation and device reproducibility remain major challenges.

Advanced transistor technologies

High-electron-mobility transistors

HEMTs use a heterojunction between two semiconductors with different band gaps (e.g., $AlGaAs/GaAs$ or $AlGaN/GaN$). At the interface, band bending creates a triangular quantum well that confines electrons in a 2D electron gas.

The key advantage: because the 2DEG forms in undoped material, electrons aren't scattered by ionized dopant atoms. This modulation doping technique yields very high carrier mobilities ($> 8000 \; \text{cm}^2/\text{V·s}$ in GaAs-based HEMTs at room temperature, compared to $\sim 1400 \; \text{cm}^2/\text{V·s}$ in bulk silicon).

HEMTs are used in satellite communication receivers, radio astronomy, and 5G base stations where low noise and high frequency operation are critical.

Organic transistors

Organic field-effect transistors (OFETs) use carbon-based semiconducting materials such as pentacene, polythiophene, or other conjugated polymers as the channel.

• Charge transport occurs through overlapping π-conjugated molecular orbitals, with carriers hopping between molecules rather than moving through a continuous band.
• Carrier mobilities are much lower than silicon (typically $0.1 - 10 \; \text{cm}^2/\text{V·s}$), so OFETs aren't suited for high-speed computing.
• Their real advantages are mechanical flexibility, large-area processing, and low fabrication cost (solution processing, printing).
• Applications include flexible displays, electronic paper, wearable health sensors, and disposable diagnostic devices.
• Stability and lifetime under ambient conditions remain active areas of research.

Carbon nanotube transistors

Single-walled carbon nanotubes (SWCNTs) are rolled-up sheets of graphene with diameters of $\sim 1 \text{ nm}$. Depending on their chirality (the angle at which the graphene sheet is rolled), they can be metallic or semiconducting.

Semiconducting SWCNTs make excellent transistor channels because of their high carrier mobility ($> 10{,}000 \; \text{cm}^2/\text{V·s}$), atomically thin body for superior electrostatic gate control, and near-ballistic transport at short channel lengths.

The main challenges are:

1. Chirality control: Separating semiconducting from metallic nanotubes during synthesis.
2. Placement: Aligning nanotubes precisely where they're needed on a chip.
3. Contact resistance: Achieving low-resistance metal-nanotube contacts.

Hybrid approaches that integrate SWCNT channels with conventional silicon CMOS processing are an active area of development.

Transistor modeling

Accurate models bridge the gap between device physics and circuit design. Without them, you can't simulate how a circuit will behave before fabrication.

Small-signal models

Small-signal models linearize the transistor's behavior around a DC operating point (bias point). They're valid only for signals small enough that the transistor's response is approximately linear.

• The hybrid-π model for BJTs represents the transistor as a voltage-controlled current source ($g_m v_{be}$) with input resistance $r_\pi = \beta / g_m$ and parasitic capacitances $C_\pi$ and $C_\mu$.
• FET small-signal models similarly include $g_m$, output resistance $r_o$, and gate capacitances $C_{gs}$ and $C_{gd}$.
• These models are essential for hand analysis of amplifier gain, input/output impedance, and bandwidth.
• They break down for large signals or highly nonlinear operating regions.

Large-signal models

Large-signal models capture the full nonlinear I-V characteristics across all operating regions.

• Gummel-Poon model: The standard BJT model, accounting for base-width modulation (Early effect), high-injection effects, and parasitic resistances.
• BSIM (Berkeley Short-channel IGFET Model): The industry-standard MOSFET model family (currently BSIM4 and BSIM-CMG for FinFETs). It includes short-channel effects, velocity saturation, gate leakage, and statistical variability.
• These models incorporate temperature dependence, noise sources, and layout-dependent effects.
• More complex models give better accuracy but slow down simulation.

SPICE simulations

SPICE (Simulation Program with Integrated Circuit Emphasis) is the industry-standard circuit simulator. It uses the transistor models described above to predict circuit behavior.

Common analysis types:

1. DC analysis: Finds the operating point (bias conditions).
2. AC analysis: Computes small-signal frequency response (gain and phase vs. frequency).
3. Transient analysis: Simulates time-domain behavior for switching and pulse response.
4. Noise analysis: Predicts noise contributions from each device.
5. Monte Carlo analysis: Runs many simulations with randomized process parameters to assess yield and variability.

SPICE is indispensable for verifying designs before committing to fabrication.

Transistor fabrication

Lithography techniques

Lithography transfers circuit patterns onto the semiconductor wafer. It's the resolution-limiting step in fabrication.

• Photolithography: UV light shines through a patterned mask onto a photoresist-coated wafer. The exposed (or unexposed, depending on resist type) regions are then removed.
• EUV lithography: Uses 13.5 nm wavelength light to print features below 10 nm. Required for leading-edge nodes (5 nm, 3 nm).
• E-beam lithography: A focused electron beam writes patterns directly, achieving sub-nm resolution. Too slow for mass production but valuable for research and mask making.
• Multi-patterning: Uses multiple lithography and etch steps to achieve feature pitches smaller than a single exposure can resolve.
• Nanoimprint lithography: Physically stamps patterns into a resist layer. Promising for cost-effective high-resolution patterning.

Etching and deposition

After lithography defines the pattern, etching removes material and deposition adds it.

Etching:

• Dry etching (reactive ion etching, plasma etching): Uses ionized gases to etch anisotropically (straight down), producing vertical sidewalls needed for small features.
• Wet etching: Uses chemical solutions. Highly selective (etches one material without affecting another) but isotropic (etches in all directions), limiting its use for fine features.

Deposition:

• CVD (Chemical Vapor Deposition): Gaseous precursors react on the wafer surface to form thin films. Used for oxides, nitrides, and polysilicon.
• ALD (Atomic Layer Deposition): Deposits one atomic layer at a time by alternating precursor gases. Gives angstrom-level thickness control, critical for gate dielectrics.
• PVD (Physical Vapor Deposition): Sputtering or evaporation deposits metals for contacts and interconnects.

Packaging and testing

Once transistors are fabricated on the wafer, they must be tested, diced, and packaged.

1. Wafer-level testing: Probe needles contact each die to run electrical tests, identifying defective chips before further processing.
2. Dicing: The wafer is cut into individual dies.
3. Bonding: Wire bonding or flip-chip solder bumps connect the die's pads to the package leads.
4. Packaging: The die is enclosed in a protective package that also provides thermal dissipation and electrical connections to the circuit board.
5. Reliability and burn-in testing: Devices are stressed at elevated temperature and voltage to screen out early failures, especially for high-reliability applications (automotive, aerospace).

Transistor scaling

Moore's law

Moore's law is the observation (not a physical law) that transistor density on integrated circuits roughly doubles every 18 to 24 months. Gordon Moore first noted this trend in 1965, and it has guided semiconductor industry roadmaps for decades.

Scaling transistors smaller brings several benefits: faster switching (shorter channel means shorter transit time), lower capacitance (less charge to move), and more functionality per chip. However, the economic cost of building fabrication facilities ("fabs") has risen dramatically. A leading-edge fab now costs upward of $20 billion, which limits how many companies can stay at the frontier.

Challenges in miniaturization

Below roughly 20 nm gate lengths, several effects threaten conventional scaling:

• Short-channel effects: The drain's electric field encroaches on the channel, reducing the gate's control. This causes threshold voltage roll-off and increased leakage.
• Gate leakage: Thinner gate oxides allow quantum tunneling, wasting power. High-k dielectrics ($HfO_2$) replaced $SiO_2$ to allow thicker physical layers while maintaining the same capacitance.
• Random dopant fluctuation: With only a handful of dopant atoms in the channel, statistical variation between transistors becomes significant, affecting yield and performance uniformity.
• Power density: Even though each transistor uses less energy, packing more transistors per area increases total heat generation. Thermal management is now a primary design constraint.
• Interconnect delay: At advanced nodes, the resistance and capacitance of the metal wires connecting transistors dominate overall circuit delay, not the transistors themselves.

These challenges have driven architectural innovations like FinFETs (3D tri-gate transistors) and gate-all-around (GAA) nanosheets, which improve electrostatic control of the channel.

Beyond silicon transistors

Research into alternative channel materials aims to extend performance scaling beyond what silicon can offer:

• III-V semiconductors ($InGaAs$, $InAs$): Electron mobilities 5-10x higher than silicon. Promising for n-channel devices but integration with silicon processing is difficult.
• Germanium: High hole mobility makes it attractive for p-channel transistors.
• 2D materials: Monolayer $MoS_2$, $WSe_2$, and other transition metal dichalcogenides have atomically thin bodies that resist short-channel effects. Graphene has extraordinary mobility but lacks a band gap, limiting its use as a switch.
• Ferroelectric gate materials: Can produce a negative capacitance effect that amplifies the gate voltage internally, potentially achieving subthreshold swings below 60 mV/decade.
• Spintronic devices: Encode information in electron spin rather than charge. Spin-transfer torque and spin-orbit torque devices could enable non-volatile logic with near-zero standby power.