🔬Condensed Matter Physics Unit 7 Review

P-n junctions are the building blocks of semiconductor devices, forming the basis for diodes, transistors, solar cells, and integrated circuits. They occur at the interface between n-type and p-type semiconductors, where the interaction of charge carriers creates unique electrical properties. Understanding how p-n junctions work is essential for grasping nearly everything else in semiconductor physics.

Fundamentals of p-n junctions

A p-n junction forms when a p-type and n-type semiconductor are brought into contact. The resulting charge carrier interactions produce a built-in electric field, a depletion region, and a voltage barrier that governs how current flows through the device.

Semiconductor doping basics

Doping means introducing impurity atoms into a semiconductor to change its electrical properties. N-type doping adds donor atoms (like phosphorus in silicon), each of which contributes a free electron to the conduction band. P-type doping adds acceptor atoms (like boron), each creating a free hole in the valence band.

Typical doping concentrations range from $10^{15}$ to $10^{19}$ cm $^{-3}$ . Higher doping means more free carriers and lower resistivity. The relative doping levels on each side of the junction directly control the depletion width, built-in potential, and breakdown voltage.

Formation of depletion region

When p-type and n-type materials are joined, carriers near the interface begin to diffuse across:

Electrons from the n-side diffuse into the p-side, leaving behind fixed positive donor ions.
Holes from the p-side diffuse into the n-side, leaving behind fixed negative acceptor ions.
These exposed ions create an electric field pointing from n to p across the junction.
The electric field opposes further diffusion, and equilibrium is reached.

The region depleted of free carriers is called the depletion region. Its width depends on the doping concentrations on each side and any externally applied voltage.

Built-in potential

The charge separation at the junction creates a built-in potential $V_{bi}$ , which acts as an energy barrier preventing majority carriers from freely crossing the junction. It's calculated as:

$V_{bi} = \frac{kT}{q} \ln\left(\frac{N_A N_D}{n_i^2}\right)$

where $N_A$ and $N_D$ are the acceptor and donor concentrations, $n_i$ is the intrinsic carrier concentration, $k$ is Boltzmann's constant, $T$ is temperature, and $q$ is the electron charge.

For silicon at room temperature, $V_{bi}$ typically falls between 0.6 and 0.7 V. This value sets the minimum forward bias needed before significant current begins to flow.

Charge carrier behavior

Current in a p-n junction results from two competing transport mechanisms, and the interplay between majority and minority carriers determines the device's electrical characteristics.

Drift and diffusion currents

Two forces drive carrier motion in a p-n junction:

Diffusion current arises from concentration gradients. Carriers naturally move from regions of high concentration to low concentration. For electrons: $J_{diff} = qD_n \frac{dn}{dx}$ . For holes: $J_{diff} = -qD_p \frac{dp}{dx}$ .
Drift current results from the electric field in the depletion region pushing carriers. For electrons: $J_{drift} = q\mu_n nE$ . For holes: $J_{drift} = q\mu_p pE$ .

At equilibrium (no applied bias), drift and diffusion currents exactly cancel, so net current is zero. Applying a voltage disrupts this balance.

Minority vs majority carriers

Majority carriers are the dominant carrier type on each side: electrons in n-type, holes in p-type. Minority carriers are the opposite: holes in n-type, electrons in p-type.

Under forward bias, minority carriers are injected across the junction. For example, electrons from the n-side are injected into the p-side, where they become minority carriers and eventually recombine with holes. This injection and recombination process is what sustains forward-bias current.

In reverse bias, the small reverse leakage current is carried almost entirely by minority carriers that are thermally generated near the junction. Minority carrier lifetime $\tau$ affects both the switching speed and the efficiency of the device.

Recombination and generation

Recombination occurs when an electron and hole annihilate each other, releasing energy as heat or light. Generation is the reverse: thermal or optical energy creates new electron-hole pairs.

Three main recombination mechanisms matter here:

Radiative recombination: the electron-hole pair recombines and emits a photon. This is the mechanism behind LEDs.
Auger recombination: the released energy is transferred to a third carrier instead of emitting a photon. Dominant at high carrier concentrations.
Shockley-Read-Hall (SRH) recombination: recombination occurs through defect states (traps) in the bandgap. This is the most common mechanism in indirect-gap semiconductors like silicon.

The carrier lifetime $\tau$ characterizes the average time a carrier survives before recombining. Generation-recombination processes within the depletion region also contribute to the reverse current.

Electrical characteristics

The current-voltage relationship of a p-n junction defines how it behaves in a circuit. This relationship is strongly nonlinear, which is what makes p-n junctions useful as rectifiers, switches, and more.

I-V curve analysis

The ideal diode equation describes the I-V characteristic:

$I = I_s\left(e^{\frac{qV}{nkT}} - 1\right)$

$I_s$ is the reverse saturation current, determined by material properties, doping, and temperature.
$n$ is the ideality factor, ranging from 1 (pure diffusion current) to 2 (recombination current dominates in the depletion region).
$V$ is the applied voltage, $k$ is Boltzmann's constant, $T$ is temperature, and $q$ is the electron charge.

Real diodes deviate from this ideal equation at high currents (due to series resistance) and at very low currents (due to generation-recombination in the depletion region).

Forward vs reverse bias

Forward bias (positive voltage on p-side) reduces the potential barrier, allowing majority carriers to cross the junction. Current increases exponentially with voltage. The typical forward voltage drop is about 0.6–0.7 V for silicon and 0.2–0.3 V for germanium.
Reverse bias (positive voltage on n-side) increases the potential barrier. Only a tiny leakage current $I_s$ flows, carried by thermally generated minority carriers. This current stays roughly constant until breakdown occurs.

Breakdown voltage

At sufficiently large reverse bias, current suddenly increases dramatically. Two mechanisms cause this:

Zener breakdown occurs in heavily doped junctions (typically below ~6 V). The strong electric field across the narrow depletion region directly pulls electrons out of covalent bonds (quantum tunneling).
Avalanche breakdown occurs in lightly doped junctions (typically above ~6 V). Carriers gain enough kinetic energy from the electric field to ionize lattice atoms on impact, creating a cascade of new carriers.

Breakdown voltage depends on doping concentration: heavier doping produces narrower depletion regions and lower breakdown voltages. Zener diodes are intentionally designed to operate in the breakdown region for voltage regulation.

Energy band diagrams

Energy band diagrams are the standard way to visualize what's happening electronically at a p-n junction. They show how the conduction band, valence band, and Fermi level vary with position.

Band bending at junction

When the junction forms, charge redistribution causes the energy bands to bend:

In the p-type region, bands bend upward (higher electron energy).
In the n-type region, bands bend downward.

This bending creates a potential energy barrier for majority carriers. The total amount of band bending equals $qV_{bi}$ , directly reflecting the built-in potential.

Fermi level alignment

At thermal equilibrium, the Fermi level must be constant throughout the entire structure. Before contact, the Fermi level sits near the conduction band in n-type material and near the valence band in p-type material. When joined, carrier diffusion and the resulting electric field shift the bands until the Fermi levels align.

Under applied bias, the system is no longer in equilibrium. The concept of quasi-Fermi levels is then used: separate Fermi levels for electrons and holes that describe the non-equilibrium carrier populations on each side.

Semiconductor doping basics, Doping: Connectivity of Semiconductors | Introduction to Chemistry

Depletion width vs bias

The depletion width $W$ depends on the applied voltage $V$ :

$W = \sqrt{\frac{2\epsilon(V_{bi} - V)}{q}\left(\frac{1}{N_A} + \frac{1}{N_D}\right)}$

Forward bias ( $V > 0$ ) shrinks the depletion region, making it easier for carriers to cross.
Reverse bias ( $V < 0$ ) widens the depletion region, increasing the barrier.

Note that $V$ is positive for forward bias in this convention, so reverse bias makes $(V_{bi} - V)$ larger. The modulation of depletion width with voltage is directly responsible for the junction's voltage-dependent capacitance.

Junction capacitance

P-n junctions store charge, so they behave partly as capacitors. This capacitance matters a great deal for high-frequency and switching applications.

Depletion capacitance

The depletion region acts like a parallel-plate capacitor: two layers of fixed charge (ionized donors and acceptors) separated by an insulating region of width $W$ . The capacitance per unit area is:

$C_d = \frac{\epsilon}{W}$

Since $W$ increases with reverse bias, depletion capacitance decreases as you apply more reverse voltage. This is the dominant capacitance contribution in reverse bias and at low forward bias. Varactor diodes exploit this voltage-dependent capacitance for tuning circuits.

Diffusion capacitance

In forward bias, minority carriers are injected across the junction and stored temporarily before they recombine. This stored charge gives rise to diffusion capacitance:

$C_{diff} = \frac{\tau I}{V_T}$

where $\tau$ is the minority carrier lifetime, $I$ is the forward current, and $V_T = kT/q$ is the thermal voltage (~26 mV at room temperature).

Diffusion capacitance is proportional to the forward current, so it dominates at moderate to high forward bias. It's the main factor limiting how fast a diode can switch off, since the stored minority carriers must recombine before the junction can block current.

Capacitance-voltage relationship

C-V measurements are a powerful characterization tool. For an abrupt junction:

$\frac{1}{C^2} = \frac{2(V_{bi} - V)}{q\epsilon}\left(\frac{N_A + N_D}{N_A N_D}\right)$

Plotting $1/C^2$ vs. $V$ gives a straight line. The slope reveals the doping concentration, and the x-intercept gives $V_{bi}$ . For non-uniform doping profiles, the slope changes with voltage, and the local doping concentration at the depletion edge can be extracted point by point.

p-n junction devices

The physics of p-n junctions enables a wide range of practical devices. Each application exploits a different aspect of junction behavior.

Diodes and LEDs

A diode is simply a p-n junction packaged for use as a circuit element. Its primary function is rectification: allowing current in one direction and blocking it in the other. Zener diodes are designed to operate in reverse breakdown for voltage regulation.

LEDs (light-emitting diodes) produce light through radiative recombination. When electrons injected into the p-side recombine with holes, they release photons with energy approximately equal to the bandgap. The semiconductor material determines the emission color: GaAs for infrared, GaN for blue/UV, and various alloys for colors in between. LED efficiency is characterized by the internal quantum efficiency (fraction of recombinations that are radiative) and external quantum efficiency (fraction of generated photons that actually escape the device).

Solar cells

Solar cells are p-n junctions that run in reverse compared to LEDs: they absorb photons and generate electrical current.

Photons with energy above the bandgap are absorbed, creating electron-hole pairs.
The built-in electric field in the depletion region separates the carriers.
Electrons are swept to the n-side and holes to the p-side, producing a photocurrent.

Performance is characterized by the open-circuit voltage $V_{oc}$ , short-circuit current $I_{sc}$ , and the fill factor. The maximum power point (MPP) is the voltage-current combination that maximizes output power. Efficiency depends on bandgap (the Shockley-Queisser limit is ~33% for a single junction), surface recombination, and optical design.

Photodetectors

Photodetectors convert light into measurable electrical signals, typically operating under reverse bias. Reverse bias widens the depletion region (increasing the photon collection volume) and strengthens the electric field (speeding up carrier separation).

PIN photodiodes insert an intrinsic (undoped) layer between p and n regions to maximize the depletion width.
Avalanche photodiodes (APDs) operate near avalanche breakdown, providing internal current gain through impact ionization.

Key performance metrics include responsivity (amperes of photocurrent per watt of incident optical power) and noise equivalent power (NEP), which indicates the minimum detectable optical signal.

Temperature effects

Temperature changes affect nearly every parameter of a p-n junction. Designing reliable circuits requires understanding these dependencies.

Reverse saturation current

The reverse saturation current $I_s$ is strongly temperature-dependent:

$I_s \propto T^3 \, e^{-E_g/kT}$

The exponential term dominates, so $I_s$ increases rapidly with temperature. A common rule of thumb: $I_s$ roughly doubles for every 10°C increase. This means leakage current can become significant at elevated temperatures, which is why precision analog circuits often need temperature compensation.

Bandgap narrowing

The bandgap energy of a semiconductor decreases as temperature rises, following the empirical Varshni relation:

$E_g(T) = E_g(0) - \frac{\alpha T^2}{T + \beta}$

where $\alpha$ and $\beta$ are material-dependent constants. For silicon, $E_g$ drops from about 1.17 eV at 0 K to 1.12 eV at 300 K. This shift affects threshold voltages, LED emission wavelengths (they red-shift at higher temperatures), and solar cell performance.

Temperature coefficient

The temperature coefficient quantifies how a parameter changes per degree of temperature change.

The forward voltage of a silicon diode has a temperature coefficient of approximately $-2$ mV/°C. As temperature rises, the forward drop decreases.
Breakdown voltage temperature coefficients depend on the mechanism: Zener breakdown (tunneling) has a negative temperature coefficient, while avalanche breakdown has a positive one.
Zener diodes designed for ~5–6 V breakdown sit right at the crossover between these mechanisms, giving a near-zero temperature coefficient. This makes them useful as voltage references.

Fabrication techniques

How a p-n junction is physically made determines its doping profile, defect density, and ultimately its performance.

Semiconductor doping basics, pn junction diode - Theory articles - Electronics-Lab.com Community

Epitaxial growth methods

Epitaxial growth deposits thin crystalline semiconductor layers on a substrate, preserving the crystal structure. Common methods include:

Molecular beam epitaxy (MBE): atoms or molecules are evaporated in ultra-high vacuum and deposited one atomic layer at a time. Offers the most precise control over thickness and composition.
Chemical vapor deposition (CVD): gaseous precursors react on the substrate surface. More scalable than MBE and widely used in industrial production.
Liquid phase epitaxy (LPE): growth from a supersaturated melt. Historically important for III-V compound semiconductors like GaAs.

Epitaxial techniques enable abrupt junctions and complex multilayer structures like quantum wells and heterojunctions.

Ion implantation

Ion implantation shoots dopant ions (accelerated to high energy) directly into the semiconductor. The process works in three steps:

Dopant ions are accelerated through a potential (typically 10 keV to several MeV) and directed at the wafer.
The ions embed at a depth controlled by the acceleration energy, with a concentration set by the beam dose.
Post-implantation annealing (heating to ~900–1100°C) activates the dopants by placing them on lattice sites and repairs the crystal damage caused by the bombardment.

Ion implantation allows selective doping through photoresist masks, making it the standard technique for CMOS fabrication.

Thermal diffusion

In thermal diffusion, the wafer is placed in a furnace at 800–1200°C with a dopant source (solid, liquid, or gas). Dopant atoms diffuse into the semiconductor from the surface, driven by the concentration gradient.

The resulting doping profile follows either a complementary error function (constant surface concentration) or a Gaussian (fixed total dose) distribution, depending on the process conditions. Thermal diffusion produces deeper junctions than ion implantation and is still used in power device and solar cell manufacturing.

Characterization methods

After fabrication, you need to verify that the junction has the intended properties. Several techniques probe different aspects of junction quality.

C-V profiling

Capacitance-voltage profiling extracts the doping concentration as a function of depth. By measuring the depletion capacitance at different reverse bias voltages, you can calculate the local doping:

$N(W) = \frac{-C^3}{q\epsilon A^2 \, dC/dV}$

where $A$ is the junction area. This technique is non-destructive and widely used in process development and quality control. The depth being probed corresponds to the depletion edge, which moves deeper into the semiconductor as reverse bias increases.

DLTS analysis

Deep Level Transient Spectroscopy (DLTS) identifies deep-level defects (traps) within the bandgap. The measurement works by:

Applying a voltage pulse to fill traps with carriers.
Returning to reverse bias and monitoring the capacitance transient as trapped carriers are thermally emitted.
Repeating at different temperatures to map out the emission rate vs. temperature.

From this data, you can extract the trap energy level, concentration, and capture cross-section. DLTS is critical for identifying recombination centers that degrade device performance.

Admittance spectroscopy

Admittance spectroscopy measures the complex admittance (conductance + capacitance) of a junction as a function of frequency and temperature. Different trap levels respond at different frequencies, so sweeping frequency reveals a spectrum of defect states.

This technique complements DLTS by being more sensitive to shallow traps and interface states. It's particularly useful for characterizing heterojunction interfaces and thin-film devices where interface quality strongly affects performance.

Advanced junction structures

Simple p-n homojunctions have limitations. Advanced structures overcome these by engineering the band structure and doping profile.

Heterojunctions vs homojunctions

A homojunction forms between the same semiconductor material with different doping (e.g., p-Si / n-Si). A heterojunction forms between two different semiconductor materials (e.g., AlGaAs / GaAs).

Heterojunctions enable band gap engineering: by choosing materials with different bandgaps, you can create band offsets that confine carriers, improve injection efficiency, or create quantum wells. Examples include AlGaAs/GaAs in high-electron-mobility transistors (HEMTs) and InGaN/GaN in blue LEDs. The tradeoff is that lattice mismatch between materials can introduce dislocations and defects at the interface.

Graded junctions

In a graded junction, the doping concentration changes gradually rather than abruptly. This creates a built-in electric field throughout the graded region (not just at the junction), which accelerates carriers and improves transport.

Graded junctions are used in:

Solar cells (to sweep photogenerated carriers more efficiently)
Bipolar transistors (graded base reduces transit time)
Power devices (graded doping increases breakdown voltage and reduces capacitance)

Abrupt vs linearly graded

Abrupt junctions have a sharp step in doping at the interface. They produce higher built-in potentials and are easier to analyze mathematically. The depletion width scales as $(V_{bi} - V)^{1/2}$ .
Linearly graded junctions have doping that changes linearly with position through the junction. They have wider depletion regions at zero bias, and the depletion width scales as $(V_{bi} - V)^{1/3}$ .

The choice between abrupt and graded profiles depends on the application. Abrupt junctions are standard in digital CMOS, while graded profiles are preferred where smooth electric field distributions reduce impact ionization or improve carrier collection.

Applications in modern electronics

Rectification and switching

Rectification (converting AC to DC) is the most basic diode application. Different diode types are optimized for different switching scenarios:

Standard p-n diodes handle general-purpose rectification in power supplies.
Fast-recovery diodes minimize the reverse recovery time, enabling high-frequency power conversion.
Schottky diodes (metal-semiconductor junctions) have lower forward voltage drops (~0.3 V) and faster switching than p-n diodes, but higher leakage.
PIN diodes are used as RF switches and variable attenuators, since their resistance in forward bias can be controlled by the injection current.

Voltage regulation

Zener diodes provide a stable reference voltage by operating in reverse breakdown. When connected in parallel with a load, the Zener clamps the voltage to its breakdown value regardless of current fluctuations (within limits).

For higher precision, bandgap reference circuits exploit the known temperature dependence of p-n junction voltages. By combining a forward-biased junction (negative temperature coefficient) with a voltage proportional to $\Delta V_{BE}$ (positive temperature coefficient), a nearly temperature-independent reference voltage of ~1.25 V (close to the silicon bandgap) can be produced.

Logic gates in ICs

P-n junctions are at the heart of every transistor, and transistors are the building blocks of logic gates.

Early diode-transistor logic (DTL) used diodes directly for input logic functions.
Transistor-transistor logic (TTL) replaced input diodes with multi-emitter bipolar transistors for faster switching.
Modern CMOS technology uses complementary pairs of n-channel and p-channel MOSFETs. Each MOSFET contains multiple p-n junctions (source-body and drain-body). CMOS dominates digital electronics because it draws almost zero static power.