11.2 ADC Architectures and Performance Metrics

ADC Architectures and Performance Metrics

Analog-to-digital converters (ADCs) bridge the gap between continuous real-world signals and the discrete digital data that processors can work with. Choosing the right ADC architecture for a biomedical application depends on tradeoffs between speed, resolution, noise, and power consumption. This section covers the major ADC architectures and the performance metrics you'll use to evaluate and compare them.

ADC Architectures

Successive Approximation ADC (SAR)

The SAR ADC uses a binary search algorithm to zero in on the digital code that best represents the analog input. Think of it like a balance scale: it starts with the most significant bit and works down, comparing the input to progressively finer reference voltages.

Here's how the conversion works:

1. The SAR logic sets the most significant bit (MSB) of an internal register to 1.
2. A DAC in the feedback loop converts that register value to an analog voltage.
3. A comparator checks whether the input signal is above or below that DAC output.
4. If the input is higher, the bit stays at 1; if lower, it's reset to 0.
5. The process repeats for each successive bit, moving from MSB to LSB.
6. After all bits are resolved, the register holds the final digital output code.

SAR ADCs offer a good balance between speed and resolution, typically achieving 8–16 bits of resolution at moderate sample rates (up to a few MSPS). They're widely used in data acquisition systems, industrial control, and many biomedical instruments like patient monitors where moderate speed and resolution are both needed.

Flash ADC

The Flash ADC (also called a parallel ADC) takes a brute-force approach: it uses a bank of comparators to evaluate the input against every possible quantization level simultaneously.

For an N-bit Flash ADC, you need $2^N - 1$ comparators, each connected to a different reference voltage set by a resistor ladder. All comparators fire at once, and a priority encoder converts their outputs into a binary code. Because everything happens in parallel, Flash ADCs are the fastest architecture available, reaching several gigasamples per second (GSPS).

The tradeoff is steep. An 8-bit Flash ADC needs 255 comparators; a 12-bit one needs 4,095. This means:

• High power consumption from all those active comparators
• Large chip area, which increases cost
• Resolution typically limited to 8–12 bits because the comparator count grows exponentially

Flash ADCs are used where speed is the top priority: radar systems, high-definition video digitization, and wideband communications receivers.

Delta-Sigma ADC (ΔΣ ADC)

Delta-Sigma ADCs take the opposite approach from Flash converters. Instead of converting fast with many bits at once, they oversample the input at a rate far above the Nyquist rate (typically 64–256×) using just a 1-bit quantizer, then use digital filtering to extract a high-resolution result.

The core loop works as follows:

1. The integrator accumulates the difference (delta) between the analog input and the feedback signal from a 1-bit DAC.
2. A comparator quantizes the integrator output into a single-bit decision (high or low).
3. That 1-bit output feeds back to the DAC, which subtracts it from the input on the next cycle.
4. This loop runs at the oversampling rate, producing a dense bitstream.
5. A digital decimation filter processes the bitstream, averaging it down to produce a high-resolution output (typically 16–24 bits) at a lower effective sample rate.

The key trick is noise shaping: the feedback loop pushes quantization noise to higher frequencies, outside the signal band of interest. The digital filter then removes that high-frequency noise.

Delta-Sigma ADCs excel in applications requiring high resolution and low noise but not high speed. They're the standard choice for audio equipment, precision measurement instruments, and biomedical applications like ECG and EEG acquisition where signal fidelity matters more than sampling speed.

Dual-Slope ADC

The Dual-Slope ADC converts by measuring time rather than directly comparing voltages. It's an integrating architecture, which gives it excellent noise rejection.

The conversion process has two phases:

1. Integration phase: The input signal charges an integrator for a fixed time interval $T_1$. The integrator output ramps up (or down) by an amount proportional to the input amplitude.
2. De-integration phase: A known reference voltage of opposite polarity is applied to the integrator. The integrator output now ramps back toward zero.
3. A counter measures the time $T_2$ it takes for the integrator to return to zero. Since $T_2$ is directly proportional to the average input voltage during $T_1$, the counter value gives the digital output.

Because the integration phase averages the input over $T_1$, periodic noise (like 50/60 Hz mains interference) can be effectively rejected by choosing $T_1$ as a multiple of the noise period. This makes Dual-Slope ADCs highly accurate for slow measurements.

Conversion speed is slow, typically a few hundred samples per second at most. You'll find these in digital multimeters, precision scales, and laboratory instruments where accuracy and noise immunity outweigh speed requirements.

Performance Metrics

Signal-to-Noise Ratio (SNR) and Dynamic Range

SNR is the ratio of signal power to noise power, expressed in decibels:

$SNR_{dB} = 10 \log_{10}\left(\frac{P_{signal}}{P_{noise}}\right)$

A higher SNR means the ADC can better resolve small signal details above the noise floor. For an ideal N-bit ADC, the theoretical maximum SNR from quantization noise alone is:

$SNR = 6.02N + 1.76 \text{ dB}$

So a perfect 12-bit ADC would have an SNR of about 74 dB.

Dynamic range is the ratio of the largest signal the ADC can handle (full-scale) to the smallest signal it can detect (noise floor), also in dB. While related to SNR, dynamic range describes the total usable amplitude window of the converter.

Factors that degrade SNR and dynamic range include:

• Quantization noise (inherent to the digitization process)
• Thermal noise from analog front-end components
• Clock jitter, which introduces timing uncertainty in the sampling instant

Effective Number of Bits (ENOB)

ENOB tells you how many bits of actual resolution an ADC delivers once you account for all real-world noise and distortion. It's calculated from the measured SNR:

$ENOB = \frac{SNR - 1.76}{6.02}$

An ideal 16-bit ADC would have an ENOB of 16. In practice, a real 16-bit ADC might have an ENOB of 13 or 14 due to circuit imperfections, noise, and distortion. That gap between the advertised bit count and the ENOB is something you should always check on a datasheet. If your application needs true 16-bit performance, you may need an ADC rated for more bits to achieve it.

Linearity: INL and DNL

Linearity describes how closely the ADC's actual transfer function matches the ideal straight-line relationship between analog input and digital output.

• Integral Nonlinearity (INL): The maximum deviation of any code transition point from the ideal straight-line transfer function, expressed in LSBs or %FSR. INL captures the overall "bowing" or curvature of the transfer function.
• Differential Nonlinearity (DNL): The difference between an actual code step width and the ideal 1 LSB step width, also in LSBs or %FSR. DNL captures local irregularities from one code to the next.

A DNL of $\pm 0.5$ LSB means each step is between 0.5 and 1.5 LSB wide, which is generally acceptable. If DNL reaches $-1$ LSB, a code can be "missing" entirely, meaning the ADC skips that digital value. Missing codes are a serious problem in precision applications.

Sources of nonlinearity include component mismatches in the DAC or resistor ladder, voltage reference drift, and comparator offset voltages.

Conversion Speed

Conversion speed (sampling rate) is the number of conversions per second, expressed in samples per second (SPS) or Hz. It directly determines the maximum input signal frequency you can digitize.

By the Nyquist-Shannon sampling theorem, you must sample at least twice the highest frequency component in the signal:

$f_s \geq 2 \cdot f_{max}$

In practice, you'll want to sample well above this minimum (often 5–10× the signal bandwidth) to ease anti-aliasing filter requirements and improve signal reconstruction.

Factors that limit conversion speed include:

• The ADC architecture itself (Flash is fastest; Dual-Slope is slowest)
• Clock frequency driving the conversion logic
• Settling time of the analog input circuitry and sample-and-hold amplifier

For biomedical signals, the required speed varies widely. ECG signals need only a few hundred to a few thousand SPS, while ultrasound imaging may require tens of MSPS or more.