14.2 Analog-to-digital and digital-to-analog conversion

Analog-to-Digital and Digital-to-Analog Conversion

Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) form the interface between continuous real-world signals and the discrete numbers that digital systems process. Every time a microcontroller reads a sensor, or a phone plays music through a speaker, a converter is doing the work. Understanding how these converters operate and what limits their performance is essential for designing signal processing systems.

Analog-to-Digital Converters

Types of ADCs and Their Functionality

An analog-to-digital converter (ADC) transforms a continuous analog voltage into a discrete digital code. Different architectures make different trade-offs between speed, resolution, and cost.

• Successive Approximation Register (SAR) ADC — Uses a binary search algorithm. It compares the input voltage against a reference, starting at the midpoint and narrowing by half each clock cycle. A 12-bit SAR ADC needs 12 comparison cycles to produce one output code. This is the workhorse architecture for moderate-speed, moderate-resolution applications.
• Flash ADC — Places $2^n - 1$ comparators in parallel (for an $n$-bit converter), each set to a different threshold voltage. All comparators fire simultaneously, so conversion happens in a single clock cycle. Flash ADCs are the fastest type but become impractical at high resolutions because the comparator count grows exponentially. Common in video processing and high-speed oscilloscopes.
• Delta-Sigma ($\Delta\Sigma$) ADC — Oversamples the input at many times the Nyquist rate and uses a feedback loop with noise shaping to push quantization noise out of the signal band. A digital decimation filter then produces a high-resolution output at a lower effective sample rate. This architecture routinely achieves 24-bit resolution and is the standard choice for audio and precision measurement.

ADC Performance Metrics

• Resolution — The number of output bits. An $n$-bit ADC divides its full-scale range into $2^n$ levels. For example, a 12-bit ADC with a 3.3 V reference has a least significant bit (LSB) size of $\frac{3.3}{2^{12}} \approx 0.806 \text{ mV}$.
• Sampling rate — The number of conversions per second (samples/s). Must satisfy the Nyquist criterion: $f_s \geq 2 f_{max}$ to avoid aliasing.
• Conversion time — The total time from the start of a conversion to a valid digital output. Shorter conversion times allow higher throughput.
• Linearity — How closely the transfer function follows an ideal straight line. Specified as differential nonlinearity (DNL) and integral nonlinearity (INL), both measured in LSBs.

ADC Applications and Trade-offs

Medical imaging systems (CT, MRI) rely on ADCs to digitize sensor outputs with high resolution and low noise. Telecommunications systems use ADCs to digitize voice and data signals for transmission over digital networks.

Choosing an ADC always involves trade-offs:

• Higher speed generally means lower achievable resolution (flash vs. delta-sigma).
• Higher resolution demands more power and longer conversion times.
• Oversampling can improve effective resolution beyond the converter's native bit count. Sampling at $4\times$ the minimum Nyquist rate gains roughly 1 extra effective bit, because averaging reduces the quantization noise floor.

Digital-to-Analog Converters

DAC Architectures and Operation

A digital-to-analog converter (DAC) takes a digital code and produces a corresponding analog voltage or current.

• Binary-weighted DAC — Uses resistors (or current sources) scaled in powers of 2. The MSB resistor carries the largest current, the next bit half as much, and so on. Simple in concept, but at high resolutions the resistor ratio between MSB and LSB becomes enormous, making precision difficult. A 12-bit binary-weighted DAC needs a $2^{11}:1$ resistor ratio.
• R-2R Ladder DAC — Uses only two resistor values, $R$ and $2R$, arranged in a ladder network. Each bit switches its $2R$ resistor between the reference voltage and ground. Because only two resistor values are needed, matching is much easier to achieve in IC fabrication. This is the most common resistive DAC topology.
• Segmented DAC — Splits the conversion into coarse and fine sections. The upper bits might use a thermometer-coded (unary) architecture for good linearity, while the lower bits use a binary-weighted section to save area. This hybrid approach balances linearity, speed, and die size.

DAC Performance Characteristics

• Linearity (DNL/INL) — Same idea as for ADCs. DNL ensures each code step is close to 1 LSB; INL measures cumulative deviation from the ideal line.
• Monotonicity — A DAC is monotonic if its output never decreases when the digital input increases. A necessary condition is that DNL is greater than $-1$ LSB everywhere.
• Settling time — The time for the output to reach and stay within a specified error band (typically $\pm\frac{1}{2}$ LSB) after a code change. This limits the maximum update rate.
• Glitch energy — Measured in pV·s or nV·s, it quantifies the area of unwanted voltage spikes that occur during code transitions, especially at major carry transitions (e.g., 0111...1 to 1000...0). Segmented architectures help reduce glitch energy.

DAC Applications and Design Considerations

Audio playback systems convert digital audio streams (e.g., 16-bit, 44.1 kHz for CD audio) back to analog through a DAC before amplification. Function generators and arbitrary waveform generators use high-speed DACs to synthesize complex analog signals from stored digital data.

Key design considerations:

• Higher resolution improves dynamic range. An $n$-bit DAC has a theoretical maximum signal-to-quantization-noise ratio of approximately $6.02n + 1.76$ dB.
• The raw DAC output is a staircase waveform. A reconstruction filter (low-pass) smooths it into a continuous signal. The filter's cutoff and order depend on the update rate and the application's spectral purity requirements.

ADC and DAC Components

Sample-and-Hold Circuit

A sample-and-hold (S/H) circuit sits in front of the ADC and freezes the input voltage so it stays constant during conversion.

1. Sample phase — The switch closes, and the hold capacitor charges to match the input voltage.
2. Hold phase — The switch opens, and the capacitor retains the captured voltage while the ADC performs its conversion.

Aperture time is the brief interval during which the switch transitions from closed to open. Uncertainty in this interval (aperture jitter) introduces noise, which becomes increasingly significant at higher input frequencies. For an input frequency $f_{in}$, the aperture jitter $\Delta t$ must satisfy $\Delta t \ll \frac{1}{2\pi f_{in} \cdot 2^n}$ to avoid degrading the effective number of bits.

Conversion Time and System Performance

Total conversion time for an ADC includes acquisition time (S/H settling), the actual conversion process, and output latency. For a DAC, it includes input register setup, internal settling, and output amplifier settling.

Pipelining is a technique where the conversion is broken into stages, each processing one or a few bits. While any single sample still takes multiple clock cycles to complete, a new sample can enter the pipeline every clock cycle. This dramatically increases throughput at the cost of added latency.

Supporting Circuitry and Signal Conditioning

• Anti-aliasing filter — A low-pass filter placed before the ADC that attenuates frequency components above $\frac{f_s}{2}$. Without it, high-frequency content folds back into the signal band and cannot be removed after sampling.
• Voltage reference — Provides the stable full-scale reference for the converter. Reference noise and drift directly affect conversion accuracy, so precision references (e.g., bandgap-based) are critical in high-resolution systems.
• Clock generation — Supplies the sampling clock. Jitter on this clock translates directly into amplitude noise on the sampled signal, especially at high input frequencies.
• Output buffers — Placed after a DAC to isolate it from varying load impedances and to provide sufficient current drive without affecting the DAC's settling behavior.