CPU Pipeline Stages

Why This Matters

Understanding CPU pipeline stages is fundamental to grasping how modern processors achieve high performance. You're being tested on concepts like instruction-level parallelism, pipeline hazards, throughput vs. latency tradeoffs, and the fetch-decode-execute cycle. These stages don't exist in isolation. They work together to allow multiple instructions to be "in flight" simultaneously, which is why a 5-stage pipeline can theoretically improve throughput by up to 5x compared to single-cycle execution.

When exam questions ask about pipeline stalls, data hazards, or control hazards, they're really testing whether you understand what each stage does and what resources it needs. Don't just memorize the stage names. Know what hardware components are active at each stage, what data flows between stages, and what happens when dependencies force the pipeline to wait. That conceptual understanding will help you tackle scenarios involving hazard detection, forwarding, and branch prediction.

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Instruction Preparation Stages

These first two stages focus on getting the instruction ready for execution: fetching it from memory and figuring out what it actually means. Both stages interact heavily with memory and control logic before any real computation happens.

Instruction Fetch (IF)

• The Program Counter (PC) holds the address of the next instruction. The CPU sends this address to instruction memory (or the instruction cache) and reads back the instruction stored there.
• The fetched instruction is placed into the Instruction Register (IR), which holds it stable while the next stage decodes it.
• The PC increments automatically (typically by 4 bytes in a 32-bit architecture like MIPS, since each instruction is 4 bytes wide). This prepares the CPU to fetch the next sequential instruction unless a branch redirects execution elsewhere.

Instruction Decode (ID)

• The opcode field is parsed to determine the operation type. This is where the control unit generates the control signals that configure every downstream stage (ALU operation, memory read/write enables, register write enable, etc.).
• The register file is read to retrieve operand values specified by the source register fields (typically $rs$ and $rt$ in MIPS). These values are latched into the ID/EX pipeline register so the next stage can use them.
• Sign extension happens here for immediate values, converting a 16-bit immediate to a full 32-bit value so it can be used in ALU operations.

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Computation and Data Stages

These middle stages perform the actual work: calculating results and accessing data memory. This is where the ALU does its job and where load/store instructions interact with the memory hierarchy.

Execute (EX)

• The ALU performs the core operation for the instruction: arithmetic ($+$, $-$), logical (AND, OR, shift), comparison, or address calculation for memory instructions.
• ALU inputs come from either two register values (R-type instructions) or one register value plus a sign-extended immediate (I-type instructions). A mux controlled by signals from ID selects the correct input.
• For branch instructions, the branch target address is calculated here by adding the sign-extended, shifted offset to the PC. This calculation happens even before the CPU knows whether the branch will be taken. That's important because it means the address is ready if the branch condition (also evaluated in EX) turns out to be true.

Memory Access (MEM)

• Data memory is accessed only for load and store instructions. All other instruction types pass through this stage doing nothing with memory. The result from EX simply flows through the EX/MEM pipeline register to the next stage.
• For loads, the effective address computed in EX is sent to data memory, and the data at that address is read out. For stores, the address is sent along with the register value to be written.
• Cache misses here create pipeline stalls, since the entire pipeline must wait for data to arrive from slower memory levels (L2 cache, L3, or main memory). This is one of the biggest sources of real-world performance loss.

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Result Completion Stage

The final stage ensures computed results become visible to future instructions. Without this stage, no instruction would ever produce a lasting change to the register file.

Write Back (WB)

• The destination register receives the result. A mux selects between the ALU output (for R-type and immediate operations) or the data loaded from memory (for load instructions), and that value is written into the register file.
• The register file write port is used here. The write register number is determined by the instruction format: $rd$ for R-type instructions, $rt$ for loads and I-type instructions.
• Store instructions skip this stage since they write to data memory, not to registers. Their work was completed in MEM. Similarly, branch instructions that don't link a return address have nothing to write back.

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Quick Reference Table

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Self-Check Questions

1. Which two stages interact with memory, and what type of memory does each access?

2. If a load instruction is followed immediately by an add instruction that uses the loaded value, at which stage is the data hazard detected, and why can't forwarding alone fix it without a one-cycle stall?

3. Compare what happens during the EX stage for an R-type arithmetic instruction versus a load word ($lw$) instruction. What's different about the ALU inputs and what the ALU result represents?

4. A store instruction ($sw$) uses the MEM stage but not the WB stage. Explain why this makes sense given what each stage does.

5. If you were implementing data forwarding to reduce stalls, which stage boundaries would need forwarding paths, and what values would be forwarded? Think about where results first become available (end of EX, end of MEM) and where they're needed (start of EX).